C8051F321-GM Silicon Laboratories Inc, C8051F321-GM Datasheet - Page 126

• Manufacturer Part Number: C8051F321-GM
• Description: IC 8051 MCU 16K FLASH 28MLP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051F32xr

Specifications of C8051F321-GM

• Program Memory Type: FLASH
• Program Memory Size: 16KB (16K x 8)
• Package / Case: 28-VQFN Exposed Pad, 28-HVQFN, 28-SQFN, 28-DHVQFN
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART, USB
• Peripherals: Brown-out Detect/Reset, POR, PWM, Temp Sensor, WDT
• Number Of I /o: 21
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 3.6 V
• Data Converters: A/D 13x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051F3x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 2.25 KB
• Interface Type: I2C/SMBus/SPI/UART/USB
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 21
• Number Of Timers: 4
• Operating Supply Voltage: 2.7 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051F320DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 13-ch x 10-bit or 17-ch x 10-bit
• No. Of I/o's: 21
• Ram Memory Size: 1280Byte
• Cpu Speed: 25MHz
• No. Of Timers: 4
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: 336-1480 - DAUGHTER CARD TOOLSTCK C8051F321770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1449 - ADAPTER PROGRAM TOOLSTICK F321336-1260 - DEV KIT FOR C8051F320/F321
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1261

C8051F320/1
14. Port Input/Output
Digital and analog resources are available through 25 I/O pins (C8051F320) or 21 I/O pins (C8051F321).
Port pins are organized as shown in Figure 14.1. Each of the Port pins can be defined as general-purpose
I/O (GPIO) or analog input; Port pins P0.0-P2.3 can be assigned to one of the internal digital resources as
shown in Figure 14.3. The designer has complete control over which functions are assigned, limited only
by the number of physical I/O pins. This resource assignment flexibility is achieved through the use of a
Priority Crossbar Decoder. Note that the state of a Port I/O pin can always be read in the corresponding
Port latch, regardless of the Crossbar settings.
The Crossbar assigns the selected internal digital resources to the I/O pins based on the Priority Decoder
(Figure 14.3 and Figure 14.4). The registers XBR0 and XBR1, defined in Figure 14.1 and Figure 14.2, are
used to select internal digital functions.
All Port I/Os are 5 V tolerant (refer to Figure 14.2 for the Port cell circuit). The Port I/O cells are configured
as either push-pull or open-drain in the Port Output Mode registers (PnMDOUT, where n = 0,1,2,3). Com-
plete Electrical Specifications for Port I/O are given in Table 14.1 on page 138.
126
Highest
Lowest
Priority
Priority
SYSCLK
Outputs
Outputs
SMBus
T0, T1
UART
P0
P1
P2
P3
PCA
CP0
CP1
SPI
Figure 14.1. Port I/O Functional Block Diagram
(P0.0-P0.7)
(P1.0-P1.7)
(P2.0-P2.7)
(P3.0)
2
4
2
2
2
6
2
8
8
8
8
Rev. 1.4
PnSKIP Registers
XBR0, XBR1,
Crossbar
Decoder
Priority
Digital
8
8
8
1
PnMDIN Registers
PnMDOUT,
Cells
Cells
Cells
Cells
Note: P2.4-P2.7 only available
I/O
I/O
I/O
I/O
P0
P1
P2
P3
on the C8051F320
P0.0
P0.7
P1.0
P1.7
P2.0
P2.7
P3.0