MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 66

• Manufacturer Part Number: MC908JB8ADWE
• Description: IC MCU 3MHZ 8K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8ADWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Configuration Register (CONFIG)
5.3 Functional Description
Technical Data
66
* URSTD and LVID bits are reset by POR or LVI reset only.
Address:
The configuration register is used in the initialization of various options.
The configuration register can be written once after each reset. Bit-5 and
bit-4 are cleared by a POR or LVI reset only. Bit-3 to bit-0 are cleared
during any reset. Since the various options affect the operation of the
MCU, it is recommended that this register be written immediately after
reset. The configuration register is located at $001F. The configuration
register may be read at any time.
URSTD — USB Reset Disable Bit
LVID — Low Voltage Inhibit Disable Bit
SSREC — Short Stop Recovery Bit
Reset:
Read:
Write:
URSTD disables the USB reset signal generating an internal reset to
the CPU and internal registers. Instead, it will generate an interrupt
request to the CPU.
LVID disables the LVI circuit
SSREC enables the CPU to exit stop mode with a delay of
2048×OSCXCLK cycles instead of a 4096×OSCXCLK cycle delay.
1 = USB reset generates a USB interrupt request to CPU
0 = USB reset generates a chip reset
1 = Disable LVI circuit
0 = Enable LVI circuit
1 = Stop mode recovery after 2048×OSCXCLK cycles
0 = Stop mode recovery after 4096×OSCXCLK cycles
$001F
Bit 7
0
0
Configuration Register (CONFIG)
Figure 5-1. Configuration Register (CONFIG)
= Unimplemented
6
0
0
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
URSTD
0*
5
LVID
0*
4
SSREC
3
0
COPRS
Freescale Semiconductor
2
0
STOP
1
0
COPD
Bit 0
0