MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 211
![IC MCU 3MHZ 8K FLASH 28-SOIC](/photos/12/16/121605/mc908jb8adwe_sml.jpg)
MC908JB8ADWE
Manufacturer Part Number
MC908JB8ADWE
Description
IC MCU 3MHZ 8K FLASH 28-SOIC
Manufacturer
Freescale Semiconductor
Series
HC08r
Datasheet
1.MC908JB8JDWE.pdf
(286 pages)
Specifications of MC908JB8ADWE
Core Processor
HC08
Core Size
8-Bit
Speed
3MHz
Connectivity
USB
Peripherals
LVD, POR, PWM
Number Of I /o
21
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
4 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
28-SOIC (7.5mm Width)
Processor Series
HC08JB
Core
HC08
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
USB
Maximum Clock Frequency
3 MHz
Number Of Programmable I/os
37
Number Of Timers
2
Operating Supply Voltage
5.25 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
Development Tools By Supplier
FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
Minimum Operating Temperature
0 C
Controller Family/series
HC08
No. Of I/o's
21
Ram Memory Size
256Byte
Cpu Speed
8MHz
No. Of Timers
1
Embedded Interface Type
SCI, SPI
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Part Number:
MC908JB8ADWE
Manufacturer:
FREESCALE
Quantity:
20 000
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12.6.2 Data Direction Register D
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
NOTE:
NOTE:
Address:
Data direction register D determines whether each port D pin is an input
or an output. Writing a logic 1 to a DDRD bit enables the output buffer for
the corresponding port D pin; a logic 0 disables the output buffer.
DDRD[7:0] — Data Direction Register D Bits
Avoid glitches on port D pins by writing to the port D data register before
changing data direction register D bits from 0 to 1.
For those devices packaged in a 20-pin PDIP and 20-pin SOIC package,
PTD7–PTD2 are not connected. DDRD7–DDRD2 should be set to a 1 to
configure PTD7–PTD2 as outputs.
For those devices packaged in a 28-pin SOIC package, PTD7 is not
connected. DDRD7 should be set to a 1 to configure PTD7 as output.
Figure 12-13
Reset:
Read:
Write:
These read/write bits control port D data direction. Reset clears
DDRD[7:0], configuring all port D pins as inputs.
Port D pins are open-drain when configured as output.
1 = Corresponding port D pin configured as output
0 = Corresponding port D pin configured as input
DDRD7
$0007
Bit 7
Figure 12-12. Data Direction Register D (DDRD)
0
shows the port D I/O circuit logic.
Input/Output Ports (I/O)
DDRD6
6
0
DDRD5
0
5
DDRD4
0
4
DDRD3
3
0
DDRD2
2
0
Input/Output Ports (I/O)
DDRD1
1
0
Technical Data
DDRD0
Bit 0
Port D
0
211
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