MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 146

• Manufacturer Part Number: MC908JB8ADWE
• Description: IC MCU 3MHZ 8K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8ADWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

Universal Serial Bus Module (USB)
9.8.6 USB Control Register 1
Technical Data
146
Address:
TP0SIZ3–TP0SIZ0 — Endpoint 0 Transmit Data Packet Size
T1SEQ — Endpoint 1 Transmit Sequence Bit
STALL1 — Endpoint 1 Force Stall Bit
TX1E — Endpoint 1 Transmit Enable
Reset:
Read:
Write:
These read/write bits store the number of transmit data bytes for the
next IN token request for endpoint 0. These bits are cleared by reset.
This read/write bit determines which type of data packet (DATA0 or
DATA1) will be sent during the next IN transaction directed to
endpoint 1. Toggling of this bit must be controlled by software. Reset
clears this bit.
This read/write bit causes endpoint 1 to return a STALL handshake
when polled by either an IN or OUT token by the USB host controller.
Reset clears this bit.
This read/write bit enables a transmit to occur when the USB host
controller sends an IN token to endpoint 1. The appropriate endpoint
enable bit, ENABLE1 bit in the UCR3 register, also should be set.
Software should set the TX1E bit when data is ready to be
transmitted. It must be cleared by software when no more data needs
to be transmitted.
1 = DATA1 token active for next endpoint 1 transmit
0 = DATA0 token active for next endpoint 1 transmit
1 = Send STALL handshake
0 = Default
T1SEQ
$003C
Bit 7
Universal Serial Bus Module (USB)
0
Figure 9-20. USB Control Register 1 (UCR1)
STALL1
6
0
MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
TX1E
5
0
FRESUM TP1SIZ3
4
0
3
0
TP1SIZ2
Freescale Semiconductor
2
0
TP1SIZ1
1
0
TP1SIZ0
Bit 0
0