MC908JB8ADWE Freescale Semiconductor, MC908JB8ADWE Datasheet - Page 43

• Manufacturer Part Number: MC908JB8ADWE
• Description: IC MCU 3MHZ 8K FLASH 28-SOIC
• Manufacturer: Freescale Semiconductor
• Series: HC08r

Specifications of MC908JB8ADWE

• Core Processor: HC08
• Core Size: 8-Bit
• Speed: 3MHz
• Connectivity: USB
• Peripherals: LVD, POR, PWM
• Number Of I /o: 21
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Oscillator Type: Internal
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 28-SOIC (7.5mm Width)
• Processor Series: HC08JB
• Core: HC08
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: USB
• Maximum Clock Frequency: 3 MHz
• Number Of Programmable I/os: 37
• Number Of Timers: 2
• Operating Supply Voltage: 5.25 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: SMD/SMT
• Development Tools By Supplier: FSICEBASE, DEMO908GZ60E, M68EML08GZE, KITUSBSPIDGLEVME, KITUSBSPIEVME, KIT33810EKEVME
• Minimum Operating Temperature: 0 C
• Controller Family/series: HC08
• No. Of I/o's: 21
• Ram Memory Size: 256Byte
• Cpu Speed: 8MHz
• No. Of Timers: 1
• Embedded Interface Type: SCI, SPI
• Rohs Compliant: Yes
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

MC68HC908JB8•MC68HC08JB8•MC68HC08JT8 — Rev. 2.3
Freescale Semiconductor
Addr.
$000C
$000D
$000A
$000B
$000E
$000F
$0010
$0011
$0012
$0013
TIM Channel 0 Status and
TIM Channel 1 Status and
TIM Status and Control
TIM Counter Register
TIM Counter Register
Register Name
TIM Counter Modulo
TIM Counter Modulo
Control Register
Control Register
Unimplemented
TIM Channel 0
TIM Channel 0
Register High
Register High
Figure 2-2. Control, Status, and Data Registers (Sheet 2 of 8)
Register Low
Register Low
(TMODH)
(TMODL)
(TCNTH)
(TCH0H)
(TCNTL)
(TCH0L)
Register
(TSC0)
(TSC1)
(TSC)
High
Low
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Reset:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Read:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
Write:
CH0F
CH1F
Bit15
Bit15
Bit15
Bit 7
TOF
Bit7
Bit7
Bit7
0
0
0
0
1
1
0
0
0
0
= Unimplemented
CH0IE
CH1IE
TOIE
Bit14
Bit14
Bit14
Bit6
Bit6
Bit6
6
0
0
0
1
1
0
0
Memory Map
TSTOP
MS0B
Bit13
Bit13
Bit13
Bit5
Bit5
Bit5
5
1
0
0
1
1
0
0
0
Indeterminate after reset
Indeterminate after reset
MS0A
MS1A
TRST
Bit12
Bit12
Bit12
Bit4
Bit4
Bit4
R
4
0
0
0
0
1
1
0
0
= Reserved
ELS0B
ELS1B
Bit11
Bit11
Bit11
Bit3
Bit3
Bit3
3
0
0
0
0
1
1
0
0
ELS0A
ELS1A
Bit10
Bit10
Bit10
PS2
Bit2
Bit2
Bit2
2
0
0
0
1
1
0
0
U = Unaffected by reset
TOV0
TOV1
PS1
Bit9
Bit1
Bit9
Bit1
Bit9
Bit1
1
0
0
0
1
1
0
0
Technical Data
Monitor ROM
Memory Map
CH0MAX
CH1MAX
Bit 0
PS0
Bit8
Bit0
Bit8
Bit0
Bit8
Bit0
0
0
0
1
1
0
0
43