C8051T614-GQ Silicon Laboratories Inc, C8051T614-GQ Datasheet - Page 210

IC 8051 MCU 8K BYTE-PROG 32-LQFP

C8051T614-GQ

Manufacturer Part Number
C8051T614-GQ
Description
IC 8051 MCU 8K BYTE-PROG 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051T61xr
Datasheets

Specifications of C8051T614-GQ

Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
29
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051FT610DK
Minimum Operating Temperature
- 40 C
On-chip Adc
21-ch x 10-bit
Package
32LQFP
Device Core
8051
Family Name
C8051T61x
Maximum Speed
25 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1441

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T614-GQ
Manufacturer:
Silicon
Quantity:
1 500
Part Number:
C8051T614-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051T614-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
C8051T610/1/2/3/4/5/6/7
C2 Register Definition 27.4. DEVCTL: C2 Device Control
C2 Address: 0x02
C2 Register Definition 27.5. EPCTL: EPROM Programming Control Register
C2 Address: 0xDF
210
Name
Reset
Name
Reset
7:0 DEVCTL[7:0] Device Control Register.
7:0 EPCTL[7:0] EPROM Programming Control Register.
Bit
Bit
Type
Type
Bit
Bit
Name
Name
7
0
7
0
This register is used to enable EPROM programming via the C2 interface. Refer to
the EPROM chapter for more information.
This register is used to halt the device for EPROM operations via the C2 interface.
Refer to the EPROM chapter for more information.
6
0
6
0
5
0
5
0
Rev 1.0
4
0
4
0
DEVCTL[7:0]
EPCTL[7:0]
R/W
R/W
Function
Function
3
0
3
0
2
0
2
0
1
0
1
0
0
0
0
0

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