C8051T614-GQ Silicon Laboratories Inc, C8051T614-GQ Datasheet - Page 118

• Manufacturer Part Number: C8051T614-GQ
• Description: IC 8051 MCU 8K BYTE-PROG 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T61xr

Specifications of C8051T614-GQ

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 29
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051FT610DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051T61x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1441

C8051T610/1/2/3/4/5/6/7
118
Pins P0.0-P2.3 are capable of being assigned to crossbar peripherals.
The crossbar peripherals are assigned in priority order from top to bottom, according to this
diagram.
enabled, the Crossbar should be manually configured to skip the corresponding port pins.
* NSS is only pinned out when the SPI is in 4-wire mode.
Pin Number
SYSCLK
Function
Pin Skip
These boxes represent Port pins which can potentially be assigned to a peripheral.
Special Function Signals are not assigned by the crossbar. When these signals are
Pins can be “skipped” by setting the corresponding bit in PnSKIP to ‘1’.
Settings
Special
Signals
Figure 21.3. Priority Crossbar Decoder Potential Pin Assignments
CP0A
CP1A
CEX0
CEX1
CEX2
CEX3
CEX4
MISO
MOSI
NSS*
SCK
SDA
RX0
SCL
CP0
CP1
Port
TX0
ECI
T0
T1
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
P0SKIP
P0
0 1 2 3 4 5 6 7
0 0 0 0 0 0 0 0
Rev 1.0
P1SKIP
P1
0 1 2 3 4 5 6 7
0 0 0 0 x x x x
P2SKIP
P2