C8051T614-GQ Silicon Laboratories Inc, C8051T614-GQ Datasheet - Page 122

• Manufacturer Part Number: C8051T614-GQ
• Description: IC 8051 MCU 8K BYTE-PROG 32-LQFP
• Manufacturer: Silicon Laboratories Inc
• Series: C8051T61xr

Specifications of C8051T614-GQ

• Program Memory Type: OTP
• Program Memory Size: 8KB (8K x 8)
• Package / Case: 32-LQFP
• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 25MHz
• Connectivity: SMBus (2-Wire/I²C), SPI, UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 29
• Ram Size: 1.25K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Processor Series: C8051T6x
• Core: 8051
• Data Bus Width: 8 bit
• Data Ram Size: 1.25 KB
• Interface Type: I2C/SPI/UART
• Maximum Clock Frequency: 25 MHz
• Number Of Programmable I/os: 29
• Number Of Timers: 4
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Development Tools By Supplier: C8051FT610DK
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 21-ch x 10-bit
• Package: 32LQFP
• Device Core: 8051
• Family Name: C8051T61x
• Maximum Speed: 25 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant
• Other names: 336-1441

C8051T610/1/2/3/4/5/6/7
SFR Definition 21.1. XBR0: Port I/O Crossbar Register 0
SFR Address = 0xE1
122
Name
Reset
Bit
Type
7
6
5
4
3
2
1
0
Bit
SYSCKE /SYSCLK Output Enable.
SMB0E
CP1AE
CP0AE
URT0E
SPI0E
Name
CP1E
CP0E
CP1AE
R/W
7
0
Comparator1 Asynchronous Output Enable.
0: Asynchronous CP1 unavailable at Port pin.
1: Asynchronous CP1 routed to Port pin.
Comparator1 Output Enable.
0: CP1 unavailable at Port pin.
1: CP1 routed to Port pin.
Comparator0 Asynchronous Output Enable.
0: Asynchronous CP0 unavailable at Port pin.
1: Asynchronous CP0 routed to Port pin.
Comparator0 Output Enable.
0: CP0 unavailable at Port pin.
1: CP0 routed to Port pin.
0: /SYSCLK unavailable at Port pin.
1: /SYSCLK output routed to Port pin.
SMBus I/O Enable.
0: SMBus I/O unavailable at Port pins.
1: SMBus I/O routed to Port pins.
SPI I/O Enable.
0: SPI I/O unavailable at Port pins.
1: SPI I/O routed to Port pins. Note that the SPI can be assigned either 3 or 4 GPIO
pins.
UART I/O Output Enable.
0: UART I/O unavailable at Port pin.
1: UART TX0, RX0 routed to Port pins P0.4 and P0.5.
CP1E
R/W
6
0
CP0AE
R/W
5
0
CP0E
R/W
Rev 1.0
4
0
Function
SYSCKE
R/W
3
0
SMB0E
R/W
2
0
SPI0E
R/W
1
0
URT0E
R/W
0
0