C8051T614-GQ Silicon Laboratories Inc, C8051T614-GQ Datasheet - Page 141

IC 8051 MCU 8K BYTE-PROG 32-LQFP

C8051T614-GQ

Manufacturer Part Number
C8051T614-GQ
Description
IC 8051 MCU 8K BYTE-PROG 32-LQFP
Manufacturer
Silicon Laboratories Inc
Series
C8051T61xr
Datasheets

Specifications of C8051T614-GQ

Program Memory Type
OTP
Program Memory Size
8KB (8K x 8)
Package / Case
32-LQFP
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), SPI, UART/USART
Peripherals
POR, PWM, WDT
Number Of I /o
29
Ram Size
1.25K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051T6x
Core
8051
Data Bus Width
8 bit
Data Ram Size
1.25 KB
Interface Type
I2C/SPI/UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
29
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051FT610DK
Minimum Operating Temperature
- 40 C
On-chip Adc
21-ch x 10-bit
Package
32LQFP
Device Core
8051
Family Name
C8051T61x
Maximum Speed
25 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1441

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
C8051T614-GQ
Manufacturer:
Silicon
Quantity:
1 500
Part Number:
C8051T614-GQ
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
Part Number:
C8051T614-GQR
Manufacturer:
Silicon Laboratories Inc
Quantity:
10 000
ARBLOST
TXMODE
MASTER
ACKRQ
STO
ACK
STA
Bit
SI
Table 22.3. Sources for Hardware Changes to SMB0CN
A START is generated.
START is generated.
SMB0DAT is written before the start of an
SMBus frame.
A START followed by an address byte is
received.
A STOP is detected while addressed as a
slave.
Arbitration is lost due to a detected STOP.
A byte has been received and an ACK
response value is needed (only when
hardware ACK is not enabled).
A repeated START is detected as a
MASTER when STA is low (unwanted
repeated START).
SCL is sensed low while attempting to
generate a STOP or repeated START
condition.
SDA is sensed low while transmitting a 1
(excluding ACK bits).
The incoming ACK value is low 
(ACKNOWLEDGE).
A START has been generated.
Lost arbitration.
A byte has been transmitted and an
ACK/NACK received.
A byte has been received.
A START or repeated START followed by a
slave address + R/W has been received.
A STOP has been received.
Set by Hardware When:
Rev 1.0
C8051T610/1/2/3/4/5/6/7
A STOP is generated.
Arbitration is lost.
A START is detected.
Arbitration is lost.
SMB0DAT is not written before the
start of an SMBus frame.
Must be cleared by software.
A pending STOP is generated.
After each ACK cycle.
Each time SI is cleared.
The incoming ACK value is high
(NOT ACKNOWLEDGE).
Must be cleared by software.
Cleared by Hardware When:
141

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