C8051F300-GM Silicon Laboratories Inc, C8051F300-GM Datasheet - Page 161
![IC 8051 MCU 8K FLASH 11QFN](/photos/12/15/121581/sl-11-mlp_sml.jpg)
C8051F300-GM
Manufacturer Part Number
C8051F300-GM
Description
IC 8051 MCU 8K FLASH 11QFN
Manufacturer
Silicon Laboratories Inc
Series
C8051F30xr
Datasheets
1.DTMFDECODER-RD.pdf
(178 pages)
2.C8051F300-TB.pdf
(2 pages)
3.C8051F300-GM.pdf
(174 pages)
Specifications of C8051F300-GM
Program Memory Type
FLASH
Program Memory Size
8KB (8K x 8)
Package / Case
11-VQFN
Core Processor
8051
Core Size
8-Bit
Speed
25MHz
Connectivity
SMBus (2-Wire/I²C), UART/USART
Peripherals
POR, PWM, Temp Sensor, WDT
Number Of I /o
8
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.6 V
Data Converters
A/D 8x8b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
C8051F3x
Core
8051
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, SMBus, UART
Maximum Clock Frequency
25 MHz
Number Of Programmable I/os
8
Number Of Timers
3 bit
Operating Supply Voltage
2.7 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Development Tools By Supplier
C8051F226DK
Minimum Operating Temperature
- 40 C
On-chip Adc
8 bit, 8 Channel
No. Of I/o's
8
Ram Memory Size
256Byte
Cpu Speed
25MHz
No. Of Timers
3
Rohs Compliant
Yes
Package
11QFN EP
Device Core
8051
Family Name
C8051F30x
Maximum Speed
25 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
770-1006 - ISP 4PORT FOR SILABS C8051F MCU336-1444 - ADAPTER PROGRAM TOOLSTICK F300336-1351 - KIT REF DES TEMP COMPENS RTC336-1348 - KIT STARTER TOOLSTICK336-1283 - KIT REF DESIGN DTMF DECODER336-1278 - KIT TOOL EVAL SYS IN A USB STICK336-1246 - DEV KIT F300/301/302/303/304/305
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
336-1245
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
C8051F300-GM
Manufacturer:
SiliconL
Quantity:
1 888
Company:
Part Number:
C8051F300-GM
Manufacturer:
TST
Quantity:
5 000
Part Number:
C8051F300-GMR
Manufacturer:
SILICON LABS/芯科
Quantity:
20 000
Note that the 8-bit offset held in PCA0CPH2 is compared to the upper byte of the 16-bit PCA counter. This
offset value is the number of PCA0L overflows before a reset. Up to 256 PCA clocks may pass before the
first PCA0L overflow occurs, depending on the value of the PCA0L when the update is performed. The
total offset is then given (in PCA clocks) by Equation 16.4, where PCA0L is the value of the PCA0L register
at the time of the update.
The WDT reset is generated when PCA0L overflows while there is a match between PCA0CPH2 and
PCA0H. Software may force a WDT reset by writing a ‘1’ to the CCF2 flag (PCA0CN.2) while the WDT is
enabled.
16.3.2. Watchdog Timer Usage
To configure the WDT, perform the following tasks:
•
•
•
•
•
The PCA clock source and Idle mode select cannot be changed while the WDT is enabled. The Watchdog
Timer is enabled by setting the WDTE or WDLCK bits in the PCA0MD register. When WDLCK is set, the
WDT cannot be disabled until the next system reset. If WDLCK is not set, the WDT is disabled by clearing
the WDTE bit.
The WDT is enabled following any reset. The PCA0 counter clock defaults to the system clock divided by
12, PCA0L defaults to 0x00, and PCA0CPL2 defaults to 0x00. Using Equation 16.4, this results in a WDT
timeout interval of 3072 system clock cycles. Table 16.3 lists some example timeout intervals for typical
system clocks, assuming SYSCLK / 12 as the PCA clock source.
Disable the WDT by writing a ‘0’ to the WDTE bit.
Select the desired PCA clock source (with the CPS2–CPS0 bits).
Load PCA0CPL2 with the desired WDT update offset value.
Configure the PCA Idle mode (set CIDL if the WDT should be suspended while the CPU is in Idle
mode).
Enable the WDT by setting the WDTE bit to ‘1’.
Equation 16.4. Watchdog Timer Offset in PCA Clocks
Offset
=
(
256 PCA0CPL2
×
Rev. 2.6
)
+
(
256 PCA0L
C8051F300/1/2/3/4/5
–
)
161