ADUC834BSZ Analog Devices Inc, ADUC834BSZ Datasheet - Page 52

• Manufacturer Part Number: ADUC834BSZ
• Description: IC ADC DUAL16/24BIT W/MCU 52MQFP
• Manufacturer: Analog Devices Inc
• Series: MicroConverter® ADuC8xxr

Specifications of ADUC834BSZ

• Core Size: 8-Bit
• Program Memory Size: 62KB (62K x 8)
• Oscillator Type: Internal
• Core Processor: 8052
• Speed: 12.58MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: POR, PSM, PWM, Temp Sensor, WDT
• Number Of I /o: 34
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 2.25K x 8
• Voltage - Supply (vcc/vdd): 2.7 V ~ 5.25 V
• Data Converters: A/D 3x16b, 4x24b; D/A 1x12b
• Operating Temperature: -40°C ~ 125°C
• Package / Case: 52-MQFP, 52-PQFP
• Controller Family/series: (8052) ADUC
• No. Of I/o's: 26
• Eeprom Memory Size: 62KB
• Ram Memory Size: 2KB
• Cpu Speed: 12.58MHz
• Package: 52MQFP
• Device Core: 8052
• Family Name: ADuC8xx
• Maximum Speed: 12.58 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 8 Bit
• Number Of Programmable I/os: 26
• Interface Type: I2C/SPI/UART
• On-chip Adc: 4-chx16-bit|4-chx24-bit
• On-chip Dac: 1-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

ADuC834
TIMERS/COUNTERS
The ADuC834 has three 16-bit Timer/Counters: Timer 0,
Timer 1, and Timer 2. The Timer/Counter hardware has been
included on-chip to relieve the processor core of the overhead
inherent in implementing timer/counter functionality in soft-
ware. Each Timer/Counter consists of two 8-bit registers THx
and TLx (x = 0, 1 and 2). All three can be configured to oper-
ate either as timers or event counters.
In ‘Timer’ function, the TLx Register is incremented every
machine cycle. Thus it can be viewed as counting machine
cycles. Since a machine cycle consists of 12 core clock periods,
the maximum count rate is 1/12 of the core clock frequency.
In ‘Counter’ function, the TLx Register is incremented by a
1-to-0 transition at its corresponding external input pin, T0,
T1, or T2. In this function, the external input is sampled during
TMOD
SFR Address
Power-On Default Value
Bit Addressable
Bit
7
6
5
4
3
2
1
0
Name
Gate
C/T
M1
M0
Gate
C/T
M1
M0
Description
Timer 1 Gating Control.
Set by software to enable timer/counter 1 only while INT1 pin is high and TR1 control bit is set.
Cleared by software to enable Timer 1 whenever TR1 control bit is set.
Timer 1 Timer or Counter Select Bit.
Set by software to select counter operation (input from T1 pin).
Cleared by software to select timer operation (input from internal system clock).
Timer 1 Mode Select Bit 1 (used with M0 Bit)
Timer 1 Mode Select Bit 0.
M1
0
0
1
1
Timer 0 Gating Control.
Set by software to enable timer/counter 0 only while INT0 pin is high and TR0 control bit is set.
Cleared by software to enable Timer 0 whenever TR0 control bit is set.
Timer 0 Timer or Counter Select Bit.
Set by software to select counter operation (input from T0 pin).
Cleared by software to select timer operation (input from internal system clock).
Timer 0 Mode Select Bit 1
Timer 0 Mode Select Bit 0.
M1
0
0
1
1
Timer/Counter 0 and 1 Mode Register
89H
00H
No
M0
0
1
0
1
M0
0
1
0
1
Table XXVI. TMOD SFR Bit Designations
TH1 operates as an 8-bit timer/counter. TL1 serves as 5-bit prescaler.
16-Bit Timer/Counter. TH1 and TL1 are cascaded; there is no prescaler.
8-Bit Auto-Reload Timer/Counter. TH1 holds a value that is to be
reloaded into TL1 each time it overflows.
Timer/Counter 1 Stopped.
TH0 operates as an 8-bit timer/counter. TL0 serves as 5-bit prescaler.
16-Bit Timer/Counter. TH0 and TL0 are cascaded; there is no prescaler
8-Bit Auto-Reload Timer/Counter. TH0 holds a value that is to be
reloaded into TL0 each time it overflows.
TL0 is an 8-bit timer/counter controlled by the standard timer 0 control
bits. TH0 is an 8-bit timer only, controlled by Timer 1 control bits.
–52–
S5P2 of every machine cycle. When the samples show a high in
one cycle and a low in the next cycle, the count is incremented.
The new count value appears in the register during S3P1 of the
cycle following the one in which the transition was detected.
Since it takes two machine cycles (16 core clock periods) to
recognize a 1-to-0 transition, the maximum count rate is 1/16 of
the core clock frequency. There are no restrictions on the duty
cycle of the external input signal, but to ensure that a given level
is sampled at least once before it changes, it must be held for a
minimum of one full machine cycle. Remember that the core
clock frequency is programmed via the CD0–2 selection bits in
the PLLCON SFR.
User configuration and control of the timers is achieved via
three main SFRs. TMOD and TCON control the configuration
of Timers 0 and 1 while T2CON configures Timer 2.
REV. A