LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 89
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
- Current page: 89 of 792
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NXP Semiconductors
UM10237_4
User manual
Table 86.
[1]
[2]
Address mappings that are not shown in
Table 87.
Bit
2:0
4:3
6:5
12:7
13
14
18:15 -
19
20
31:21 -
14
16 bit external bus high-performance address mapping (Row, Bank, Column)
0
0
0
0
0
0
The SDRAM column and row width and number of banks are computed automatically from the address
mapping.
The buffers must be disabled during SDRAM and SyncFlash initialization. They must also be disabled when
performing SyncFlash commands. The buffers must be enabled during normal operation.
12
0
0
0
0
0
0
Symbol
-
Memory device
(MD)
-
Address
mapping (AM)
-
Address
mapping (AM)
Buffer enable
(B)
Write protect (P) 0
11:9 8:7
000
000
001
001
010
010
Dynamic Memory Configuration registers (EMCDynamicConfig0-3 - address
0xFFE0 8100, 0xFFE0 8120, 0xFFE0 8140, 0xFFE0 8160) bit description
Address mapping
00
01
00
01
00
01
Description
16 MB (2Mx8), 2 banks, row length = 11, column length = 9
16 MB (1Mx16), 2 banks, row length = 11, column length = 8
64 MB (8Mx8), 4 banks, row length = 12, column length = 9
64 MB (4Mx16), 4 banks, row length = 12, column length = 8
128 MB (16Mx8), 4 banks, row length = 12, column length = 10
128 MB (8Mx16), 4 banks, row length = 12, column length = 9
Rev. 04 — 26 August 2009
-
00
01
10
11
-
0
0
0
1
1
Value Description
-
-
-
Chapter 5: LPC24XX External Memory Controller (EMC)
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
SDRAM (POR reset value).
Low-power SDRAM.
Micron SyncFlash.
Reserved.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
See
000000 = reset value.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
See
0 = reset value.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Buffer disabled for accesses to this chip select (POR
reset value).
Buffer enabled for accesses to this chip select.
Writes not protected (POR reset value).
Writes protected.
Reserved, user software should not write ones to
reserved bits. The value read from a reserved bit is not
defined.
Table 5–87
Table 5–87
Table 5–87
[1]
are reserved.
UM10237
© NXP B.V. 2009. All rights reserved.
[2]
89 of 792
Reset
Value
NA
00
NA
0
NA
0
NA
0
NA
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