LPC2470FBD208,551 NXP Semiconductors, LPC2470FBD208,551 Datasheet - Page 438
![IC ARM7 MCU LCD 208-LQFP](/photos/12/13/121391/208-lqfp_sot459-1_pkg_sml.jpg)
LPC2470FBD208,551
Manufacturer Part Number
LPC2470FBD208,551
Description
IC ARM7 MCU LCD 208-LQFP
Manufacturer
NXP Semiconductors
Series
LPC2400r
Datasheets
1.OM11077.pdf
(792 pages)
2.LPC2470FET208551.pdf
(89 pages)
3.LPC2470FET208551.pdf
(91 pages)
Specifications of LPC2470FBD208,551
Package / Case
208-LQFP
Core Processor
ARM7
Core Size
16/32-Bit
Speed
72MHz
Connectivity
CAN, EBI/EMI, Ethernet, I²C, Microwire, MMC, SPI, SSI, SSP, UART/USART, USB OTG
Peripherals
Brown-out Detect/Reset, DMA, I²S, LCD, POR, PWM, WDT
Number Of I /o
160
Program Memory Type
ROMless
Ram Size
98K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 8x10b; D/A 1x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
LPC24
Core
ARM7TDMI-S
Data Bus Width
16 bit, 32 bit
Data Ram Size
98 KB
Interface Type
CAN/I2C/I2S/SPI/SSP/UART/USB
Maximum Clock Frequency
72 MHz
Number Of Programmable I/os
160
Number Of Timers
4
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
MDK-ARM, RL-ARM, ULINK2, MCB2470U
Minimum Operating Temperature
- 40 C
On-chip Adc
8-ch x 10-bit
On-chip Dac
1-ch x 10-bit
Package
208LQFP
Device Core
ARM7TDMI-S
Family Name
LPC2000
Maximum Speed
72 MHz
Operating Supply Voltage
3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Other names
568-4361-5
935284068551
LPC2470FBD208-S
935284068551
LPC2470FBD208-S
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LPC2470FBD208,551
Manufacturer:
NXP Semiconductors
Quantity:
10 000
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NXP Semiconductors
UM10237_4
User manual
4.12.1 Baudrate calculation
Table 392. UARTn Fractional Divider Register (U0FDR - address 0xE000 C028,
This register controls the clock pre-scaler for the baud rate generation. The reset value of
the register keeps the fractional capabilities of UART0/2/3 disabled making sure that
UART0/2/3 is fully software and hardware compatible with UARTs not equipped with this
feature.
UART0/2/3 baudrate can be calculated as (n = 0/2/3):
Where PCLK is the peripheral clock, U0/2/3DLM and U0/2/3DLL are the standard
UART0/2/3 baud rate divider registers, and DIVADDVAL and MULVAL are UART0/2/3
fractional baudrate generator specific parameters.
The value of MULVAL and DIVADDVAL should comply to the following conditions:
The value of the U0/2/3FDR should not be modified while transmitting/receiving data or
data may be lost or corrupted.
If the U0/2/3FDR register value does not comply to these two requests, then the fractional
divider output is undefined. If DIVADDVAL is zero then the fractional divider is disabled,
and the clock will not be divided.
UART can operate with or without using the Fractional Divider. In real-life applications it is
likely that the desired baudrate can be achieved using several different Fractional Divider
settings. The following algorithm illustrates one way of finding a set of DLM, DLL,
MULVAL, and DIVADDVAL values. Such set of parameters yields a baudrate with a
relative error of less than 1.1% from the desired one.
Bit
3:0
7:4
31:8 -
1. 1 ≤ MULVAL ≤ 15
2. 0 ≤ DIVADDVAL ≤ 14
3. DIVADDVAL< MULVAL
Function
DIVADDVAL
MULVAL
U2FDR - 0xE007 8028, U3FDR - 0xE007 C028) bit description
UARTn
baudrate
Value Description
0
1
NA
Rev. 04 — 26 August 2009
=
Baud-rate generation pre-scaler divisor value. If this field is
0, fractional baud-rate generator will not impact the UARTn
baudrate.
Baud-rate pre-scaler multiplier value. This field must be
greater or equal 1 for UARTn to operate properly,
regardless of whether the fractional baud-rate generator is
used or not.
Reserved, user software should not write ones to reserved
bits. The value read from a reserved bit is not defined.
----------------------------------------------------------------------------------------------------------------------------------
16
×
(
256
×
UnDLM
+
PCLK
UnDLL
Chapter 16: LPC24XX UART0/2/3
)
×
⎛
⎝
1
+
DivAddVal
---------------------------- -
MulVal
UM10237
© NXP B.V. 2009. All rights reserved.
⎞
⎠
438 of 792
Reset
value
0
1
0
(2)
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