P89LPC922FDH,512 NXP Semiconductors, P89LPC922FDH,512 Datasheet - Page 46

• Manufacturer Part Number: P89LPC922FDH,512
• Description: IC 80C51 MCU FLASH 8K 20-TSSOP
• Manufacturer: NXP Semiconductors
• Series: LPC900r

Specifications of P89LPC922FDH,512

• Core Processor: 8051
• Core Size: 8-Bit
• Speed: 18MHz
• Connectivity: I²C, UART/USART
• Peripherals: Brown-out Detect/Reset, LED, POR, PWM, WDT
• Number Of I /o: 18
• Program Memory Size: 8KB (8K x 8)
• Program Memory Type: FLASH
• Ram Size: 256 x 8
• Voltage - Supply (vcc/vdd): 2.4 V ~ 3.6 V
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 20-TSSOP
• Processor Series: P89LPC9x
• Core: 80C51
• Data Bus Width: 8 bit
• Data Ram Size: 256 B
• Interface Type: I2C, UART
• Maximum Clock Frequency: 18 MHz
• Number Of Programmable I/os: 18
• Number Of Timers: 2
• Operating Supply Voltage: 2.4 V to 3.6 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: PK51, CA51, A51, ULINK2
• Minimum Operating Temperature: - 40 C
• For Use With: 622-1014 - BOARD FOR LPC9XX TSSOP622-1010 - BOARD FOR LPC922 TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDEPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details
• Other names: 568-2452; 935273788512; P89LPC922FDH

Philips Semiconductors
Contents
1
2
2.1
2.2
3
3.1
4
5
5.1
5.2
6
7
8
8.1
8.2
8.2.1
8.2.2
8.2.3
8.2.4
8.2.5
8.2.6
8.3
8.4
8.5
8.6
8.7
8.8
8.9
8.10
8.11
8.11.1
8.12
8.12.1
8.12.2
8.12.3
8.12.4
8.12.5
8.12.6
8.12.7
8.13
8.13.1
8.13.2
8.14
8.14.1
8.14.2
8.14.3
8.15
8.15.1
8.16
8.16.1
8.16.2
8.16.3
8.16.4
© Koninklijke Philips Electronics N.V. 2004.
Printed in the U.S.A.
All rights are reserved. Reproduction in whole or in part is prohibited without the prior
written consent of the copyright owner.
The information presented in this document does not form part of any quotation or
contract, is believed to be accurate and reliable and may be changed without notice. No
liability will be accepted by the publisher for any consequence of its use. Publication
thereof does not convey nor imply any license under patent- or other industrial or
intellectual property rights.
Date of release: 15 December 2004
General description . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Ordering information . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
Pinning information. . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Logic symbol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8
Special function registers. . . . . . . . . . . . . . . . . . . . . . 9
Functional description . . . . . . . . . . . . . . . . . . . . . . . 14
Principal features . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . . 2
Ordering options . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3
Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5
Pin description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
Enhanced CPU . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clocks . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
Clock definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14
CPU clock (OSCCLK) . . . . . . . . . . . . . . . . . . . . . . . 14
Low speed oscillator option . . . . . . . . . . . . . . . . . . . 14
Medium speed oscillator option . . . . . . . . . . . . . . . . 14
High speed oscillator option . . . . . . . . . . . . . . . . . . . 14
Clock output . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
On-chip RC oscillator option . . . . . . . . . . . . . . . . . . 15
Watchdog oscillator option . . . . . . . . . . . . . . . . . . . . 15
External clock input option . . . . . . . . . . . . . . . . . . . . 15
CPU Clock (CCLK) wake-up delay. . . . . . . . . . . . . . 17
CPU Clock (CCLK) modification: DIVM register . . . 17
Low power select . . . . . . . . . . . . . . . . . . . . . . . . . . . 17
Memory organization . . . . . . . . . . . . . . . . . . . . . . . . 17
Data RAM arrangement . . . . . . . . . . . . . . . . . . . . . . 18
Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
External interrupt inputs . . . . . . . . . . . . . . . . . . . . . . 18
I/O ports . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Port configurations . . . . . . . . . . . . . . . . . . . . . . . . . . 19
Quasi-bidirectional output configuration. . . . . . . . . . 20
Open-drain output configuration. . . . . . . . . . . . . . . . 20
Input-only configuration . . . . . . . . . . . . . . . . . . . . . . 20
Push-pull output configuration . . . . . . . . . . . . . . . . . 20
Port 0 analog functions . . . . . . . . . . . . . . . . . . . . . . 20
Additional port features . . . . . . . . . . . . . . . . . . . . . . 21
Power monitoring functions . . . . . . . . . . . . . . . . . . . 21
Brownout detection . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power-on detection . . . . . . . . . . . . . . . . . . . . . . . . . 21
Power reduction modes . . . . . . . . . . . . . . . . . . . . . . 21
Idle mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Power-down mode . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Total Power-down mode . . . . . . . . . . . . . . . . . . . . . . 22
Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
Reset vector . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Timers/counters 0 and 1 . . . . . . . . . . . . . . . . . . . . . 23
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Document order number: 9397 750 14469
8.16.5
8.16.6
8.17
8.18
8.18.1
8.18.2
8.18.3
8.18.4
8.18.5
8.18.6
8.18.7
8.18.8
8.18.9
8.18.10
8.19
8.20
8.20.1
8.20.2
8.20.3
8.21
8.22
8.23
8.23.1
8.23.2
8.24
8.24.1
8.24.2
8.24.3
8.25
8.26
9
10
11
12
13
14
15
16
17
18
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Limiting values . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35
Static characteristics . . . . . . . . . . . . . . . . . . . . . . . . . 36
Dynamic characteristics . . . . . . . . . . . . . . . . . . . . . . 38
Comparator electrical characteristics . . . . . . . . . . . 41
Package outline . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42
Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
Data sheet status . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Definitions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Licenses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45
Mode 6 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Timer overflow toggle output. . . . . . . . . . . . . . . . . . . 24
Real-Time clock/system timer. . . . . . . . . . . . . . . . . . 24
UART . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mode 0 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
Mode 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Mode 3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Baud rate generator and selection . . . . . . . . . . . . . . 25
Framing error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25
Break detect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Double buffering . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
Transmit interrupts with double buffering
The 9
I
Analog comparators . . . . . . . . . . . . . . . . . . . . . . . . . 29
Internal reference voltage . . . . . . . . . . . . . . . . . . . . . 29
Comparator interrupt. . . . . . . . . . . . . . . . . . . . . . . . . 30
Comparators and power reduction modes . . . . . . . . 30
Keypad interrupt (KBI) . . . . . . . . . . . . . . . . . . . . . . . 30
Watchdog timer. . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Additional features . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Software reset. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Dual data pointers. . . . . . . . . . . . . . . . . . . . . . . . . . . 31
Flash program memory. . . . . . . . . . . . . . . . . . . . . . . 32
General description. . . . . . . . . . . . . . . . . . . . . . . . . . 32
Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
ISP and IAP capabilities of
User configuration bytes . . . . . . . . . . . . . . . . . . . . . . 34
User sector security bytes . . . . . . . . . . . . . . . . . . . . 34
enabled (Modes 1, 2 and 3) . . . . . . . . . . . . . . . . . . . 26
3) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26
2
the P89LPC920/921/922/9221 . . . . . . . . . . . . . . . . 32
C-bus serial interface . . . . . . . . . . . . . . . . . . . . . . . 27
th
bit (bit 8) in double buffering (Modes 1, 2 and