P89LPC922FDH,512 NXP Semiconductors, P89LPC922FDH,512 Datasheet - Page 20

IC 80C51 MCU FLASH 8K 20-TSSOP

P89LPC922FDH,512

Manufacturer Part Number
P89LPC922FDH,512
Description
IC 80C51 MCU FLASH 8K 20-TSSOP
Manufacturer
NXP Semiconductors
Series
LPC900r
Datasheet

Specifications of P89LPC922FDH,512

Core Processor
8051
Core Size
8-Bit
Speed
18MHz
Connectivity
I²C, UART/USART
Peripherals
Brown-out Detect/Reset, LED, POR, PWM, WDT
Number Of I /o
18
Program Memory Size
8KB (8K x 8)
Program Memory Type
FLASH
Ram Size
256 x 8
Voltage - Supply (vcc/vdd)
2.4 V ~ 3.6 V
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
20-TSSOP
Processor Series
P89LPC9x
Core
80C51
Data Bus Width
8 bit
Data Ram Size
256 B
Interface Type
I2C, UART
Maximum Clock Frequency
18 MHz
Number Of Programmable I/os
18
Number Of Timers
2
Operating Supply Voltage
2.4 V to 3.6 V
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
PK51, CA51, A51, ULINK2
Minimum Operating Temperature
- 40 C
For Use With
622-1014 - BOARD FOR LPC9XX TSSOP622-1010 - BOARD FOR LPC922 TSSOP622-1008 - BOARD FOR LPC9103 10-HVSON622-1006 - SOCKET ADAPTER BOARDEPM900K - EMULATOR/PROGRAMMER NXP P89LPC9568-4000 - DEMO BOARD SPI/I2C TO DUAL UART568-3510 - DEMO BOARD SPI/I2C TO UART622-1002 - USB IN-CIRCUIT PROG LPC9XX568-1759 - EMULATOR DEBUGGER/PROGRMMR LPC9X
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Data Converters
-
Lead Free Status / Rohs Status
 Details
Other names
568-2452
935273788512
P89LPC922FDH
Philips Semiconductors
9397 750 14469
Product data
8.12.2 Quasi-bidirectional output configuration
8.12.3 Open-drain output configuration
8.12.4 Input-only configuration
8.12.5 Push-pull output configuration
8.12.6 Port 0 analog functions
P1.2 (SCL/T0) and P1.3 (SDA/INT0) may only be configured to be either input-only or
open-drain.
Quasi-bidirectional output type can be used as both an input and output without the
need to reconfigure the port. This is possible because when the port outputs a logic
HIGH, it is weakly driven, allowing an external device to pull the pin LOW. When the
pin is driven LOW, it is driven strongly and able to sink a fairly large current. These
features are somewhat similar to an open-drain output except that there are three
pull-up transistors in the quasi-bidirectional output that serve different purposes.
The P89LPC920/921/922/9221 is a 3 V device, but the pins are 5 V-tolerant. In
quasi-bidirectional mode, if a user applies 5 V on the pin, there will be a current
flowing from the pin to V
5 V in quasi-bidirectional mode is discouraged.
A quasi-bidirectional port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
The open-drain output configuration turns off all pull-ups and only drives the
pull-down transistor of the port driver when the port latch contains a logic ‘0’. To be
used as a logic output, a port configured in this manner must have an external
pull-up, typically a resistor tied to V
An open-drain port pin has a Schmitt-triggered input that also has a glitch
suppression circuit.
The input-only port configuration has no output drivers. It is a Schmitt-triggered input
that also has a glitch suppression circuit.
The push-pull output configuration has the same pull-down structure as both the
open-drain and the quasi-bidirectional output modes, but provides a continuous
strong pull-up when the port latch contains a logic ‘1’. The push-pull mode may be
used when more source current is needed from a port output. A push-pull port pin
has a Schmitt-triggered input that also has a glitch suppression circuit. The
P89LPC9221 device has high source current on eight pins in push-pull mode. See
Table 8 “DC electrical
The P89LPC920/921/922/9221 incorporates two Analog Comparators. In order to
give the best analog function performance and to minimize power consumption, pins
that are being used for analog functions must have the digital outputs and digital
inputs disabled.
Digital outputs are disabled by putting the port output into the Input-Only (high
impedance) mode as described in
Digital inputs on Port 0 may be disabled through the use of the PT0AD register,
bits 1:5. On any reset, PT0AD1:5 defaults to ‘0’s to enable digital functions.
Rev. 08 — 15 December 2004
characteristics”.
DD
, causing extra power consumption. Therefore, applying
P89LPC920/921/922/9221
8-bit microcontrollers with two-clock 80C51 core
Section
DD
.
8.12.4.
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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