AT89C5132-ROTUL Atmel, AT89C5132-ROTUL Datasheet
AT89C5132-ROTUL
Specifications of AT89C5132-ROTUL
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AT89C5132-ROTUL Summary of contents
Page 1
... TQFP80, PLCC84 (Development Board Only) – Dice 1. Description The AT89C5132 is a mass storage device controlling data exchange between various Flash modules, HDD and CD-ROM. The AT89C5132 includes 64K Bytes of Flash memory and allows In-System Program- ming through an embedded 4K Bytes of Boot Flash Memory. ...
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... Block Diagram Figure 3-1. AT89C5132 Block Diagram INT0 INT1 Interrupt Handler Unit RAM 2304 Bytes C51 (X2 CORE) Clock and PLL Unit FILT X1 X2 RST DOUT Notes: 1. Alternate function of Port 3 2. Alternate function of Port 4 3. Alternate function of Port 1 AT89C5132 2 AV UVSS AVSS ...
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... Pin Description Figure 4-1. 4173E–USB–09/07 AT89C5132 80-pin TQFP Package ALE 1 ISP 2 P1.0/KIN0 3 P1.1/KIN1 4 P1.2/KIN2 5 P1.3/KIN3 6 P1.4 7 P1.5 8 P1.6/SCL 9 P1.7/SDA 10 VDD 11 PVDD 12 FILT 13 PVSS 14 VSS TST 18 UVDD 19 UVSS 20 AT89C5132 TQFP80 P4.5 P4.4 P2.2/A10 P2.3/A11 P2.4/A12 P2.5/A13 P2.6/A14 P2.7/A15 VSS VDD ...
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... Figure 4-2. Note: 4.1 Signals All the AT89C5132 signals are detailed by functionality in Table 1 to Table 14. Table 1. Ports Signal Description Signal Name P0.7:0 P1.7:0 AT89C5132 4 (1) AT89C5132 84-pin PLCC ALE 12 ISP 13 P1.0/KIN0 14 P1.1/KIN1 15 P1.2/KIN2 16 P1.3/KIN3 17 P1.4 18 P1.5 19 P1.6/SCL 20 P1.7/SDA 21 VDD 22 PAVDD 23 FILT ...
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... INT1 serves as external run control for timer 1, when selected by GATE1 bit in TCON register. I External Interrupt 1 INT1 input sets IE1 in the TCON register. If bit IT1 in this register is set, bit IE1 is set by a falling edge on INT1. If bit IT1 is cleared, bit IE1 is set by a low level on INT1. AT89C5132 Alternate Function A15:8 RXD TXD INT0 ...
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... Signal Name D+ D- Table 6. MutiMediaCard Interface Signal Description Signal Name MCLK MCMD MDAT AT89C5132 6 Type Description Timer 0 External Clock Input I When timer 0 operates as a counter, a falling edge on the T0 pin increments the count. Timer 1 External Clock Input I When timer 1 operates as a counter, a falling edge on the T1 pin increments the count ...
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... I/O SDA is the bidirectional Two Wire data line. Type Description I A/D Converter Analog Inputs I Analog Positive Voltage Reference Input Analog Negative Voltage Reference Input I This pin is internally connected to AVSS. AT89C5132 Alternate Function P3.0 P3.1 Alternate Function P4.0 P4.1 P4.2 P4.3 Alternate Function P1 ...
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... Name A15:8 AD7:0 ALE ISP RD WR Table 13. System Signal Description Signal Name RST TST AT89C5132 8 Type Description Keypad Input Lines I Holding one of these pins high or low for 24 oscillator periods triggers a keypad interrupt. Type Description Address Lines I/O Upper address lines for the external bus. ...
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... Connect this pin to ground. PLL Supply voltage PWR Connect this pin to +3V supply voltage. PLL Circuit Ground GND Connect this pin to ground. USB Supply Voltage PWR Connect this pin to +3V supply voltage. USB Ground GND Connect this pin to ground. AT89C5132 Alternate Function - - - - - - - - 9 ...
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... Internal Pin Structure Table 15. Detailed Internal Pin Structure Latch Output Notes: AT89C5132 10 (1) Circuit VDD VDD Watchdog Output P VSS VDD 2 osc periods VSS VDD P N VSS VDD P N VSS For information on resistors value, input/output levels, and drive capability, refer to the Section “ ...
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... ISP. It also contains some Application Programming Interfaces routines commonly known as API allowing user to develop his own bootloader. 5.0.3 Data Memory The AT89C5132 derivatives implement 2304 bytes of on-chip data RAM. This memory is divided in two separate areas: • 256 bytes of on-chip RAM memory (standard C51 memory). ...
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... Oscillator The AT89C5132 X1 and X2 pins are the input and the output of a single-stage on-chip inverter (see Figure 6-1) that can be configured with off-chip components such as a Pierce oscillator (see Figure 6-2). Value of capacitors and crystal characteristics are detailed in the Section “DC Characteristics” ...
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... The X2 bit reset value depends on the X2B bit in the Hardware Security Byte (see Table 12 on page 24). Using the AT89C5132 (Flash Version) the system can boot either in standard or X2 mode depending on the X2B value. Using AT83C51SND1C (ROM Version) the system always boots in standard mode ...
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... The PLL clock frequency will depend on the audio interface clock frequencies. Figure 6-6. 6.4 Registers Table 1. CKCON Register AT89C5132 14 PLL Block Diagram and Symbol PLLCON.1 PLLEN N divider ...
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... Clear to select 12 clock periods per machine cycle (STD mode, F Set to select 6 clock periods per machine cycle (X2 mode Bit Mnemonic Description Reserved - The value read from this bit is always 0. Do not set this bit. PLL N Divider N6:0 7-bit N divider. AT89C5132 T1X2 T0X2 = F CPU PER = CPU PER OSC 3 2 ...
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... R1 Bit Number Reset Value = 0000 1000b Table 4. PLLRDIV Register PLLRDIV (S:EFh) – PLL R Divider Register 7 R9 Bit Number Reset Value = 0000 0000b AT89C5132 Bit Mnemonic Description PLL Least Significant Bits R Divider R1:0 2 LSB of the 10-bit R divider. Reserved - The values read from these Bits are always 0. Do not set these Bits. ...
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... In Application Programming (IAP) by using user’s own bootloader. Figure 7-1. 7.1 Flash Memory Architecture As shown in Figure 7-2 the AT89C5132 Flash memory is composed of four spaces detailed in the following paragraphs. Figure 7-2. 4173E–USB–09/07 voltage, made possible by the internal charge pump. Thus, the ...
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... This byte is used to lock the execution of some bootloader commands. 7.2 Hardware Security System The AT89C5132 implements three lock Bits LB2:0 in the LSN of HSB (see Table 7) providing three levels of security for user’s program as described in Table 7 while the AT83C51SND1C is always set in read disabled mode. ...
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... Figure 7-3, when this bit is programmed (by hardware or software programming mode), the chip resets ENBOOT and forces the reset vector to F000h instead of 0000h, in order to execute the bootloader software. Figure 7-3. Hardware Boot Process Algorithm The software process (bootloader) is detailed in the AT89C5132 Bootloader datasheet. 4173E–USB–09/07 RESET Hard Cond? ISP = L? ...
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... Reset Value = XXXX 00X0b 7.5 Hardware Bytes Table 7. HSB Byte – Hardware Security Byte 7 X2B Bit Number AT89C5132 ENBOOT - Bit Mnemonic Description Reserved - The values read from these Bits are indeterminate. Do not set these Bits. Enable Boot Flash Set this bit to map the boot Flash in the code space between at addresses F000h to ENBOOT FFFFh ...
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... Mnemonic Description Hardware Lock Bits LB2:0 Refer to for bits description. 1. X2B initializes the X2 bit in CKCON during the reset phase order to ensure boot loader activation at first power-up, AT89C5132 products are delivered with BLJB programmed. 3. Bits (LSN) can only be programmed by hardware mode ADD14 ...
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... Data Memory The AT89C5132 provides data memory access in two different spaces: 1. The internal space mapped in three separate segments: – – – 2. The external space. A fourth internal segment is available but dedicated to Special Function Registers, SFRs, (addresses 80h to FFh) accessible by direct addressing mode. For information on this segment, refer to the section “ ...
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... Bytes Lower 128 Bytes RAM, Upper 128 Bytes RAM, and expanded RAM are made of volatile memory cells. This means that the RAM content is indeterminate after power-up and must then be initial- ized properly. AT89C5132 7Fh 2Fh Bit-Addressable Space (Bit Addresses 0 - 7Fh) ...
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... WR 8.2.2 Page Access Mode The AT89C5132 implement a feature called Page Access that disables the output of DPH on P2 when executing MOVX @DPTR instruction. Page Access is enable by setting the DPHDIS bit in AUXR register. Page Access is useful when application uses both ERAM and 256 Bytes of XRAM. In this case, software modifies intensively EXTRAM bit to select access to ERAM or XRAM and must save it if used in interrupt service routine ...
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... CPU Clock ALE ( DPL signal may be stretched using M0 bit in AUXR register. 2. When executing MOVX @Ri instruction, P2 outputs SFR content. 3. When executing MOVX @DPTR instruction, if DPHDIS is set (Page Access Mode), P2 out- puts SFR content instead of DPH. AT89C5132 D7:0 (2),(3) DPH or P2 D7:0 (2),(3) DPH ...
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... Dual Data Pointer 8.3.1 Description The AT89C5132 implement a second data pointer for speeding up code execution and reducing code size in case of intensive usage of external memory accesses. DPTR0 and DPTR1 are seen by the CPU as DPTR and are accessed using the SFR addresses 83h and 84h that are the DPH and DPL addresses. The DPS bit in AUXR1 register (see Table 15) is used to select whether DPTR is the data pointer 0 or the data pointer 1 (see Figure 8-6) ...
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... Clear not to stretch signals and set duration to 3 CPU clock periods. DPH Disable Bit DPHDIS Set to disable DPH output on P2 when executing MOVX @DPTR instruction. Clear to enable DPH output on P2 when executing MOVX @DPTR instruction. Expanded RAM Size Bits XRS1:0 Refer to Table 11 for ERAM size description. AT89C5132 RS0 ...
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... Bit Number 1 0 Reset Value = X000 1101b AT89C5132 28 Bit Mnemonic Description External RAM Enable Bit Set to select the external XRAM when executing MOVX @Ri or MOVX @DPTR EXTRAM instructions. Clear to select the internal expanded RAM when executing MOVX @Ri or MOVX @DPTR instructions. ...
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... Special Function Registers The Special Function Registers (SFRs) of the AT89C5132 derivatives fall into the categories detailed in Table 15 to Table 30. The relative addresses of these SFRs are provided together with their reset values in Table 31. In this table, the bit-addressable registers are identified by Note 1. ...
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... WatchDog Timer Reset WDTPRG A7h WatchDog Timer Program Table 22. Audio Interface SFRs Mnemonic Add Name AUDCON0 9Ah Audio Control 0 AUDCON1 9Bh Audio Control 1 AUDSTA 9Ch Audio Status AUDDAT 9Dh Audio Data AUDCLK ECh Audio Clock Divider AT89C5132 FPL3 FPL2 FPL1 FPL0 TF1 ...
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... EORI EOCI EOFI MCBM EORM EOCM EOFM MC7 MC6 MC5 MC4 MD7 MD6 MD5 MD4 MMCD7 MMCD6 MMCD5 MMCD4 D15 D14 D13 D12 AT89C5132 UPRSM RMWUPE CONFG FADDEN UADD3 UADD2 UADD1 UADD0 SOFINT - - SPINT - - ESPINT - - EPNUM1 EPNUM0 DTGL EPDIR EPTYPE1 EPTYPE0 ...
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... Keyboard Control KBSTA A4h Keyboard Status Table 30. A/D Controller SFRs Mnemonic Add Name ADCON F3h ADC Control ADCLK F2h ADC Clock Divider ADDL F4h ADC Data Low Byte ADDH F5h ADC Data High Byte AT89C5132 FE/SM0 SM1 SM2 REN - - - BRR SPR2 SPEN ...
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... Reserved Notes: 1. SFR registers with least significant nibble address equal are bit-addressable. 2. NVERS reset value depends on the silicon version: 1000 0011 for AT89C5132 product 3. FCON register is only available in AT89C5132 product. 4. FCON reset value is 00h in case of reset with hardware condition. 5. CKCON reset value depends on the X2B bit (programmed or unprogrammed) in the Hardware Byte. ...
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... Interrupt System Priorities Each of the interrupt sources on the AT89C5132 can be individually programmed to one of four priority levels. This is accomplished by one bit in the Interrupt Priority High registers (IPH0 and IPH1) and one bit in the Interrupt Priority Low registers (IPL0 and IPL1). This provides each interrupt source four possible priority levels according to Table 33 ...
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... IPLxx Priority Number 0 (Highest Priority (Lowest Priority) AT89C5132 Priority Level 0 Lowest Highest Interrupt Request Flag Cleared by Hardware (H) Interrupt Address Vectors or by Software (S) C:0003h H if edge level C:000Bh C:0013h H if edge level C:001Bh C:0023h C:0033h C:003Bh C:0043h C:004Bh C:0053h C:005Bh C:0063h C:006Bh ...
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... INT0 Interrupt 0 Timer 0 External INT1 Interrupt 1 Timer 1 TXD Serial Port RXD Audio Interface MCLK MMC MDAT Controller MCMD SCL Two-wire Controller SDA SCK SPI SI Controller AIN1:0 Converter KIN3:0 Keyboard D+ USB Controller D- AT89C5132 EX0 00 IEN0 ET0 00 IEN0 EX1 00 IEN0 ET1 00 IEN0 IEN0 ...
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... Edge-triggered external interrupts must hold the request pin low for at least 6 peripheral clock periods. Figure 10-3. Minimum Pulse Timings 4173E–USB–09/07 INT0 IT0/1 TCON.0/2 Level-Triggered Interrupt Edge-Triggered Interrupt 1 cycle AT89C5132 INT0/1 Interrupt IE0/1 Request TCON.1/3 EX0/1 IEN0.0/2 > 1 peripheral cycle 1 cycle > 1 peripheral cycle 1 cycle ...
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... EA Bit Number Reset Value = 0000 0000b Table 36. IEN1 Register IEN1 (S:B1h) – Interrupt Enable Register AT89C5132 EAUD – ES Bit Mnemonic Description Enable All Interrupt Bit Set to enable all interrupts. Clear to disable all interrupts each interrupt source is individually enabled or disabled by setting or clearing its interrupt enable bit ...
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... ESPI Set to enable SPI interrupt. Clear to disable SPI interrupt. Two Wire Controller Interrupt Enable Bit EI2C Set to enable Two Wire interrupt. Clear to disable Two Wire interrupt. MMC Interface Interrupt Enable Bit EMMC Set to enable MMC interrupt. Clear to disable MMC interrupt. AT89C5132 39 ...
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... Table 10- Bit Number Reset Value = X000 0000b AT89C5132 40 IPH0 Register IPH0 (S:B7h) – Interrupt Priority High Register IPHAUD – IPHS Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Audio Interface Interrupt Priority Level MSB IPHAUD Refer to Table 33 for priority level description ...
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... SPI Interrupt Priority Level MSB IPHSPI Refer to Table 33 for priority level description. Two Wire Controller Interrupt Priority Level MSB IPHI2C Refer to Table 33 for priority level description. MMC Interrupt Priority Level MSB IPHMMC Refer to Table 33 for priority level description. AT89C5132 IPHADC IPHSPI IPHI2C 0 IPHMMC ...
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... Table 38. IPL0 Register IPL0 (S:B8h) – Interrupt Priority Low Register Bit Number Reset Value = X000 0000b AT89C5132 IPLAUD – IPLS Bit Mnemonic Description Reserved - The value read from this bit is indeterminate. Do not set this bit. Audio Interface Interrupt Priority Level LSB IPLAUD Refer to Table 33 for priority level description ...
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... SPI Interrupt Priority Level LSB IPLSPI Refer to Table 33 for priority level description. Two Wire Controller Interrupt Priority Level LSB IPLI2C Refer to Table 33 for priority level description. MMC Interrupt Priority Level LSB IPLMMC Refer to Table 33 for priority level description. AT89C5132 IPLADC IPLSPI IPLI2C 0 IPLMMC ...
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... Power Management 2 power reduction modes are implemented in the AT89C5132: the Idle mode and the Power- down mode. These modes are detailed in the following sections. In addition to these power reduction modes, the clocks of the core and peripherals can be dynamically divided by 2 using the X2 mode detailed in Section “X2 Feature”, page 12. ...
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... If the time between 2 on/off DD sequences is too fast, the power-supply de-coupling capacitors may not be fully discharged, leading to a bad reset sequence. VDD + RST VDD 1K RST VSS AT89C5132 (1) VDD Rise Time 10 ms 1.2 µF 3.9 µF VDD From WDT Reset Source P To CPU Core ...
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... Note: AT89C5132 46 If IDL bit and PD bit are set simultaneously, the AT89C5132 enter Power-down mode. Then it does not go in Idle mode when exiting Power-down mode. Hardware clears IDL bit in PCON register which restores the clock to the CPU. Execution resumes with the interrupt service routine. Upon completion of the interrupt service routine, program execution resumes with the instruction immediately following the instruction that activated Idle mode ...
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... Entering Power-down Mode To enter Power-down mode, set PD bit in PCON register. The AT89C5132 enters the Power- down mode upon execution of the instruction that sets PD bit. The instruction that sets PD bit is the last instruction executed. 11.4.2 Exiting Power-down Mode If V was reduced during the Power-down mode, do not exit Power-down mode until V DD restored to the normal operating level ...
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... Power-down mode and may continue for a number of clock cycles before the internal reset algorithm takes control. Reset initializes the AT89C5132 and vectors the CPU to address 0000h. 1. During the time that execution resumes, the internal RAM cannot be accessed; however possible for the Port pins to be accessed ...
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... Timers/Counters The AT89C5132 implement two general-purpose, 16-bit Timers/Counters. They are identified as Timer 0 and Timer 1, and can be independently configured to operate in a variety of modes as a Timer event Counter. When operating as a Timer, the Timer/Counter runs for a pro- grammed length of time, then issues an interrupt request. When operating as a Counter, the Timer/Counter counts negative transitions on an external pin ...
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... TH0 register. Figure 12-3 gives the overflow period calculation formula. Figure 12-2. Timer/Counter Mode 0 TIMx ÷ 6 CLOCK Tx C/Tx# TMOD Reg INTx GATEx TMOD Reg TCON Reg Figure 12-3. Mode 0 Overflow Period Formula AT89C5132 50 PER 0 CLOCK Timer 0 Clock 1 OSC CLOCK T0X2 0 TLx (5 Bits) ...
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... TCON Reg ⋅ 6 (65536 – (THx, TLx)) TFx = PER F TIMx 0 1 TRx TCON Reg 6 ⋅ (256 – THx) TFx = PER F TIMx AT89C5132 TLx Overflow TFx (8 Bits) TCON Reg TLx Overflow TFx (8 Bits) TCON Reg THx (8 Bits) Timer x Interrupt Request Timer x Interrupt Request 51 ...
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... For this situation, use Timer 1 only for applications that do not require an interrupt (such as a Baud Rate Generator for the Serial Port) and switch Timer 1 in and out of mode 3 to turn it off and on. • important to stop the Timer/Counter before changing modes. AT89C5132 Bits) 1 TR0 TCON ...
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... Interrupts are enabled by setting ETx bit in IEN0 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 12-10. Timer Interrupt System 4173E–USB–09/07 TF0 TCON.5 ET0 IEN0.1 TF1 TCON.7 ET1 IEN0.3 AT89C5132 Timer 0 Interrupt Request Timer 1 Interrupt Request 53 ...
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... Bit Number Reset Value = 0000 0000b Table 41. TMOD Register TMOD (89:h) - Timer/Counter 0 and 1 Modes 7 GATE1 AT89C5132 TR1 TF0 TR0 Bit Mnemonic Description Timer 1 Overflow Flag TF1 Cleared by hardware when processor vectors to interrupt routine. Set by hardware on Timer/Counter overflow, when Timer 1 register overflows. ...
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... Mode 1: 16-bit Timer/Counter. M00 1 0 Mode 2: 8-bit auto-reload Timer/Counter (TL0 Mode 3: TL0 is an 8-bit Timer/Counter. TH0 is an 8-bit Timer using Timer 1’s TR0 and TF0 Bits. 1. Reloaded from TH1 at overflow. 2. Reloaded from TH0 at overflow Bit Mnemonic Description High Byte of Timer 0 AT89C5132 (1) ( ...
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... Table 44. TH1 Register TH1 (S:8Dh) – Timer 1 High Byte Register 7 - Bit Number 7:0 Reset Value = 0000 0000b Table 45. TL1 Register TL1 (S:8Bh) – Timer 1 Low Byte Register 7 - Bit Number 7:0 Reset Value = 0000 0000b AT89C5132 Bit Mnemonic Description Low Byte of Timer ...
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... Watchdog Timer The AT89C5132 implement a hardware Watchdog Timer (WDT) that automatically resets the chip allowed to time out. The WDT provides a means of recovering from routines that do not complete successfully due to software or hardware malfunctions. 13.1 Description The WDT consists of a 14-bit prescaler followed by a 7-bit programmable counter. As shown in Figure 13-1, the 14-bit prescaler is fed by the WDT clock detailed in section " ...
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... WDT Behavior During Idle and Power-down Modes Operation of the WDT during power reduction modes deserves special attention. The WDT continues to count while the AT89C5132 are in Idle mode. This means that the user must dedicate some internal or external hardware to service the WDT during Idle mode. One approach is to use a peripheral Timer to generate an interrupt request when the Timer over- flows ...
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... Reset Value = XXXX X000b 4173E–USB–09/ Bit Mnemonic Description - Watchdog Control Value Bit Mnemonic Description Reserved - The values read from these Bits are indeterminate. Do not set these Bits. Watchdog Timer Time-Out Selection Bits WTO2:0 Refer to Table 46 for time-out periods. AT89C5132 WTO2 WTO1 WTO0 59 ...
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... Audio Output Interface The AT89C5132 implement an audio output interface allowing the audio bitstream to be output in various formats compatible with right and left justification PCM and I thanks to the on-chip PLL (see Section “Clock Controller”, page 12) allows connection of almost all of the commercial audio DAC families available on the market. ...
Page 61
... PCM LSB justified 20-bit PCM MSB justified 4173E–USB–09/07 AUDCLK PLL AUCD4:0 CLOCK AUDclk POL = 0 Left Channel POL = 1 Left Channel 2 S AT89C5132 Audio Interface Clock CLOCK Audio Clock Symbol PLLclk = --------------------------- AUCD + 1 Right Channel Right Channel 2 S format, JUST4:0 bits in AUDCON0 register ...
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... Section "Interrupt Request", page 63. The buffer size is 8 Bytes large. SREQ is set when the samples number switches from and reset when the samples number switches from UNDR is set when the buffer becomes empty signaling that the audio interface ran out of samples; and AUBUSY is set when the buffer is full. AT89C5132 62 Left Channel 3 ...
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... One sample duplication, DAC rate = 16 kHz (2 x C51 rate). 0 Two samples duplication, DAC rate = 32 kHz (4 x C51 rate). 1 Three samples duplication, DAC rate = 48 kHz (6 x C51 rate). UDRN AUDSTA.6 MUDRN AUDCON1.4 SREQ AUDSTA.7 MSREQ AUDCON1.5 AT89C5132 Audio Interrupt Request EAUD IEN0.6 63 ...
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... JUST4 Bit Number 7 Reset Value = 0000 1000b Table 52. AUDCON1 Register AUDCON1 (S:9Bh) – Audio Interface Control Register 1 7 – AT89C5132 64 Audio Interrupt Service Routine Wait for DAC Enable Time Sample Request? Load 8 Samples in the Audio Buffer Load 4 Samples in the Audio Buffer ...
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... Set in C51 audio source mode when the audio interface cannot accept more sample AUBUSY (buffer full). Cleared by hardware when buffer is no more full. Reserved - The value read from these bits is always 0. Do not set these bits AUD6 AUD5 AUD4 AT89C5132 AUD3 AUD2 AUD1 ...
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... Bit Number 7-0 Reset Value = 1111 1111b Table 55. AUDCLK Register AUDCLK (S:ECh) – Audio Clock Divider Register 7 - Bit Number 7-5 4-0 Reset Value = 0000 0000b AT89C5132 66 Bit Mnemonic Description Audio Data AUD7:0 8-bit sampling data for voice or sound playing AUCD4 Bit ...
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... Two different configurations and descriptor sets are used to support DFU functions. The Run-Time configuration co-exist with the usual functions of the device, which shall be USB Mass Storage for AT89C5132 used to initiate DFU from the normal operating mode. The DFU configuration is used to perform the firmware update after device re- configuration and USB reset ...
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... The Universal Function Interface (UFI) controls the interface between the data flow and the Dual Port RAM, but also the interface with the C51 core itself. Figure 15-3 shows how to connect the AT89C5132 to the USB connector. D+ and D- pins are connected through 2 termination resistors. A pull-up resistor is implemented inform the host of a full speed device connection. Value of these resistors is detailed in the section “ ...
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... Detector NRZI ‘ NRZ Bit Unstuffing Packet Bit Counter Clock SysClk 48 MHz (12 MHz) Recover USB Pattern Generator Parallel to Serial Converter Bit Stuffing NRZI Converter CRC16 Generator AT89C5132 48 MHz USB Clock PLLclk USBclk = ------------------------------- - USBCD + 1 SYNC Detector PID Decoder Address Decoder 8 Serial to Parallel ...
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... Function Interface Unit (UFI) The Function Interface Unit provides the interface between the AT89C5132 and the SIE. It man- ages transactions at the packet level with minimal intervention from the device firmware, which reads and writes the endpoint FIFOs. Figure 15-6 shows typical USB IN and OUT transactions reporting the split in the hardware (UFI) and software (C51) load ...
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... STLCRC: Stall Sent Interrupt Flag/CRC Error Interrupt Flag. This flag triggers an interrupt after a STALL handshake has been sent on the bus, for Control, Bulk and Interrupt endpoints. This flag triggers an interrupt when the last data received is corrupted for Isochronous endpoints. 4173E–USB–09/07 AT89C5132 71 ...
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... WUPCPU USBINT.5 EWUPCPU USBIEN.5 EORINT USBINT.4 EEORINT USBIEN.4 SOFINT USBINT.3 ESOFINT USBIEN.3 SPINT USBINT.0 ESPINT USBIEN.0 15.3 Registers Table 56. USBCON Register USBCON (S:BCh) – USB Global Control Register AT89C5132 72 EPxINT UEPINT.x EPxIE UEPIEN USBE SUSPCLK SDRMWUP USB interrupt EUSB IEN1 UPRSM ...
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... Set by the device firmware after a successful status phase of a SET_ADDRESS transaction. It shall not be cleared afterwards by the device 0 FADDEN firmware. Cleared by hardware on hardware reset or when an USB reset is received. When this bit is cleared, the default function address is used (0 FEN UADD6 UADD5 AT89C5132 UADD4 UADD3 UADD2 UADD1 1 0 UADD0 73 ...
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... Reset Value = 0000 0000b Table 58. USBINT Register USBINT (S:BDh) – USB Global Interrupt Register Reset Value = 0000 0000b Table 59. USBIEN Register USBIEN (S:BEh) – USB Global Interrupt Enable Register AT89C5132 74 Bit Bit Number Mnemonic Description Function Enable Bit Set to enable the function. The device firmware shall set this bit after it has ...
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... The values read from these Bits are always 0. Do not set these Bits. Endpoint Number Bits EPNUM1:0 Set this field with the number of the endpoint which shall be accessed when reading or writing to registers UEPSTAX, UEPDATX, UBYCTLX or UEPCONX EPEN - - AT89C5132 EPNUM1 DTGL EPDIR ...
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... Reset Value = 0000 0000b Table 62. UEPSTAX Register UEPSTAX (Soh) – USB Endpoint X Status and Control Register (X = EPNUM set in UEPNUM) AT89C5132 76 Bit Bit Number Mnemonic Description Endpoint Enable Bit Set to enable the endpoint according to the device configuration. Endpoint 0 shall 7 EPEN always be enabled after a hardware or USB bus reset and participate in the device configuration ...
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... Set by hardware after an IN packet has been transmitted for Isochronous endpoints and after it has been accepted (ACK’ed) by the host for Control, Bulk 0 TXCMP and Interrupt endpoints. Then, the endpoint interrupt is triggered if enabled in UEPIEN. Clear by software before setting again TXRDY AT89C5132 EP3RST EP2RST EP1RST 0 EP0RST 77 ...
Page 78
... Reset Value = 0000 0000b Table 64. UEPINT Register UEPINT (S:F8h Read-only) – USB Endpoint Interrupt Register Reset Value = 0000 0000b Table 65. UEPIEN Register UEPIEN (S:C2h) – USB Endpoint Interrupt Enable Register AT89C5132 78 Bit Bit Number Mnemonic Description Reserved The values read from these Bits are always 0. Do not set these Bits. ...
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... Reserved 7 - The values read from this Bits are always 0. Do not set this bit. Byte Count 6-0 BYCT7:0 Byte count of a received data packet. This byte count is equal to the number of data Bytes received after the Data PID. AT89C5132 FDAT3 FDAT2 FDAT1 4 ...
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... UFNUML (S:BAh, Read-only) – USB Frame Number Low Register Reset Value = 00h Table 69. UFNUMH Register UFNUMH (S:BBh, Read-only) – USB Frame Number High Register Reset Value = 00h Table 70. USBCLK Register USBCLK (S:EAh) – USB Clock Divider Register AT89C5132 FNUM7 FNUM6 FNUM5 ...
Page 81
... Reset Value = 0000 0000b 4173E–USB–09/07 Bit Bit Number Mnemonic Description USB Controller Clock Divider USBCD1:0 2-bit divider for USB controller clock generation. AT89C5132 81 ...
Page 82
... MultiMedia Card Controller The AT89C5132 implements a MultiMedia Card (MMC) controller. The MMC is used to store files in removable Flash memory cards that can be easily plugged or removed from the application. 16.1 Card Concept The basic MultiMedia Card concept is based on transferring data via a minimal number of signals ...
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... MCMD line similarly to the stream read. Figure 16-1 to Figure 16-5 show the different types of operations, on these figures, grayed tokens are from host to card(s) while white tokens are from card(s) to host. 4173E–USB–09/07 and – used to supply the cards. SS1 SS2 DD AT89C5132 83 ...
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... Command MDAT Figure 16-4. (Multiple) Block Write Operation MCMD Command Response MDAT Figure 16-5. No Response and No Data Operation MCMD MDAT AT89C5132 84 Command Response Data Transfer Operation Response Data Block CRC Data Block CRC Data Block CRC Multiple Block Read Operation Response ...
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... Value ‘0’ ‘1’ Transmission Start bit Description bit R1, R4 Content Total Length = 48 Bits Content Total Length = 48 Bits Content = CID or CSD AT89C5132 CRC 1 45:40 39:8 7 Command Argument CRC7 Index CRC 1 1 CRC Total Length = 136 Bits 0 1 ‘1’ ...
Page 86
... Each data packet is preceded by a Start bit: a low level on MCMD line and suc- ceeded by an End bit: a high level on MCMD line. Due to the fact that there is no predefined end AT89C5132 86 Bit Position ...
Page 87
... MDAT (formally the MMC DAT) line traffic to or from the card, and the interrupt controller that handles the MMC controller interrupt sources. These blocks are detailed in the following sections. 4173E–USB–09/07 Sequential Data 0 Block Data 0 AT89C5132 Content Content CRC Block Length ...
Page 88
... MCMD line and the command receiver channel that handles the response reception from the card through the MCMD line. These channels are detailed in the following sections. AT89C5132 88 Clock Command Line ...
Page 89
... Data Converter CRC7 // -> Serial Generator TX COMMAND Line Finished State Machine CMDEN MMCON1.0 MMSTA.2 MMSTA.1 CRC7S RESPFS Data Converter CRC7 and Format Serial -> // Checker RX COMMAND Line Finished State Machine RESPEN RFMT CRCDIS MMCON1.1 MMCON0.1 MMCON0.0 AT89C5132 MMINT.5 EOCI MCMD MMINT.6 EORI 89 ...
Page 90
... CCR bit in MMCON2 register. This timeout may be disarmed when receiving the response. 16.6 Data Line Controller The data line controller is based on a 16-byte FIFO used both by the data transmitter channel and by the data receiver channel. AT89C5132 90 Command Transmission Load Command in Buffer ...
Page 91
... Serial Generator DATA Line Finished State Machine DFMT MBLOCK DATEN MMCON0.2 MMCON0.3 MMCON1.2 BLEN3:0 Block Length (Byte) BLEN = 0000 to 1011 Length = 2 > 1011 Reserved: do not program BLEN3:0 > 1011 AT89C5132 MDAT CRC16 MMINT.4 EOFI DATDIR BLEN3:0 MMCON1.3 MMCON1.7:4 BLEN : 1 to 2048 91 ...
Page 92
... Two other flags in MMSTA register: DATFS and CRC16S report a status on the frame sent. DATFS indicates if the CRC status token format is correct or not, and CRC16S indicates if the card has found the CRC16 of the block correct or not. AT89C5132 92 Data Stream Data Single Block ...
Page 93
... Transmission ISR FIFOs Filling FIFO Empty? Write 16 Data to MMDAT F1EI or F2EI = 1? Unmask FIFOs Empty F1EM = 0 F2EM = 0 FIFO Filling Write 8 Data to MMDAT Start Transmission DATEN = 1 No More Data DATEN = 0 To Send? Mask FIFOs Empty STOP Command b. Interrupt Mode AT89C5132 F1EM = 1 F2EM = 1 Send 93 ...
Page 94
... According to the MMC specification data transmission, the card starts after the access time delay (formally N locking of the MMC controller when card does not send its data (e.g. physically removed from the bus), the user must launch a time-out period to exit from such situation. In case of time-out AT89C5132 94 Data Block Initialization ...
Page 95
... Polling Mode 4173E–USB–09/07 Data Stream Data Stream Initialization Reception ISR Unmask FIFOs Full FIFO Full? F1FM = 0 F1FI or F2FI = 1? F2FM = 0 FIFO Reading read 8 data from MMDAT No More Data To Receive? Mask FIFOs Full F1FM = 1 F2FM = 1 Send STOP Command b. Interrupt Mode AT89C5132 95 ...
Page 96
... MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These flags were detailed in the previous sections. All of these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM, F1FM, and F2EM mask bits, respectively, in MMMSK register. AT89C5132 96 Data Block Data Block ...
Page 97
... DRPTR DTPTR CRPTR CTPTR Bit Bit Number Mnemonic Description Data Receive Pointer Reset Bit 7 DRPTR Set to reset the read pointer of the data FIFO. Clear to release the read pointer of the data FIFO. AT89C5132 MMC Interface Interrupt Request EMMC IEN1 MBLOCK DFMT RFMT 0 ...
Page 98
... Reset Value = 0000 0000b Table 79. MMCON1 Register MMCON1 (S:E5h) – MMC Control Register 1 Reset Value = 0000 0000b Table 80. MMCON2 Register AT89C5132 98 Bit Bit Number Mnemonic Description Data Transmit Pointer Reset Bit 6 DTPTR Set to reset the write pointer of the data FIFO. Clear to release the write pointer of the data FIFO. ...
Page 99
... The values read from these Bits are always 0. Do not set these Bits. Card Busy Flag 5 CBUSY Set by hardware when the card sends a busy state on the data line. Cleared by hardware when the card no more sends a busy state on the data line. AT89C5132 ...
Page 100
... Reset Value = 0000 0000b Table 82. MMINT Register MMINT (S:E7h Read Only) – MMC Interrupt Register AT89C5132 100 Bit Bit Number Mnemonic Description CRC16 Status Bit Transmission mode Set by hardware when the token response reports a good CRC. 4 CRC16S Cleared by hardware when the token response reports a bad CRC. ...
Page 101
... Set to prevent EOFI flag from generating an MMC interrupt. Clear to allow EOFI flag to generate an MMC interrupt. FIFO 2 Full Interrupt Mask Bit 3 F2FM Set to prevent F2FI flag from generating an MMC interrupt. Clear to allow F2FI flag to generate an MMC interrupt. AT89C5132 EOFM F2FM F1FM F2EM ...
Page 102
... Reset Value = 1111 1111b Table 84. MMCMD Register MMCMD (S:DDh) – MMC Command Register Reset Value = 1111 1111b AT89C5132 102 Bit Bit Number Mnemonic Description FIFO 1 Full Interrupt Mask Bit 2 F1FM Set to prevent F1FI flag from generating an MMC interrupt. Clear to allow F1FI flag to generate an MMC interrupt. ...
Page 103
... MMC Data Byte MD7:0 Input (write) or output (read) register of the data FIFO MMCD7 MMCD6 MMCD5 MMCD4 Bit Bit Number Mnemonic Description MMC Clock Divider MMCD7:0 8-bit divider for MMC clock generation. AT89C5132 MD4 MD3 MD2 MD1 MMCD3 MMCD2 MMCD1 1 0 MD0 1 0 ...
Page 104
... IDE/ATAPI Interface The AT89C5132 provide an IDE/ATAPI interface allowing connection of devices such as CD- ROM reader, CompactFlash cards, hard disk drive, etc. It consists of a 16-bit data transfer (read or write) between the AT89C5132 and the IDE devices. 17.1 Description The IDE interface mode is enabled by setting the EXT16 bit in AUXR (see As soon as this bit is set, all MOVX instructions read or write are done in a 16-bit mode compare to the standard 8-bit mode ...
Page 105
... Figure 17-3 and Figure 17-4 show two examples on how to interface up to two IDE devices to the AT89C5132. In both examples P0 carries IDE low order data bits D7:0, P2 carries IDE high order data bits D15:8, while RD and WR signals are respectively connected to the IDE nIOR and nIOW signals ...
Page 106
... Table 88. DAT16H Register DAT16H (S:F9h) – Data 16 High Order Byte 7 D15 Bit Number Reset Value = 0000 0000b AT89C5132 106 Type Description Address Lines I/O Upper address lines for the external bus. Multiplexed higher address and data lines for the IDE interface. ...
Page 107
... Serial I/O Port The serial I/O port in the AT89C5132 provides both synchronous and asynchronous communi- cation modes. It operates as a Synchronous Receiver and Transmitter in one single mode (Mode 0) and operates as an Universal Asynchronous Receiver and Transmitter (UART) in three full-duplex modes (modes 1, 2 and 3). Asynchronous modes support framing error detection and multiprocessor communication with automatic address recognition ...
Page 108
... The 8-bit data are transmitted and received least-significant bit (LSB) first. Shifts occur at a fixed Baud Rate (see Section "Baud Rate Selection (Mode 0)", page 110). Figure 18-3 shows the serial port block dia- gram in Mode 0. AT89C5132 108 PER ÷ 6 ...
Page 109
... RI bit to indicate a completed reception. Software can then read the received byte from SBUF register. 4173E–USB–09/07 SCON.6 SCON.7 SM1 SM0 Mode Decoder Mode Controller TI RI SCON.1 SCON.0 TXD RXD AT89C5132 SBUF Tx SR SBUF Rx SR Baud Rate Controller RXD TXD 109 ...
Page 110
... As shown in Figure 18-6, the selection is done using M0SRC bit in BDRCON register. Figure 18-7 gives the baud rate calculation formulas for each baud rate source. Figure 18-6. Baud Rate Source Selection (mode 0) Figure 18-7. Baud Rate Formulas (Mode 0) AT89C5132 110 TXD Set REN, Clear RI ...
Page 111
... SCON.6 SCON.7 SM1 SM0 Mode Decoder CLOCK Mode & Clock IBRG Controller CLOCK PER CLOCK SM2 TI SCON.4 SCON.1 Mode Start bit Start bit AT89C5132 SCON.3 TB8 SBUF SBUF Rx RI SCON 8-bit data 9-bit data TXD RXD RB8 SCON.2 Stop bit D8 ...
Page 112
... Figure 18-13 gives the baud rate calculation formulas for each baud rate source. Table 90 details Internal Baud Rate Generator configuration for different peripheral clock frequencies and gives baud rates closer to the standard baud rates. Figure 18-12. Baud Rate Source Selection (Modes 1 and 3) AT89C5132 112 Framing Error FE ...
Page 113
... SPD 1 BRL % SPD - - - - 243 0. 236 2. 217 0. 178 0. 100 0. ÷ 2. PER OSC = F . PER OSC AT89C5132 SMOD1 2 Baud_Rate= 6 ⋅ 32 ⋅ (256 -TH1) SMOD1 2 TH1= 256 - 192 ⋅ Baud_Rate b. T1 Formula ( MHz MHz PER PER SMOD Error SMOD 1 BRL % SPD 247 3. 243 0. 230 0.16 ...
Page 114
... SM2 bit in SCON register. When the multiprocessor communication feature is enabled, the Serial Port can differentiate between data frames (ninth bit clear) and address frames (ninth bit set). This allows the AT89C5132 to function as a slave processor in an environ- ment where multiple slave processors share a single serial line. ...
Page 115
... SADEN = 1111 1001b Given = 1111 0XX1b SADEN = 1111 1101b Given = 1111 00X1b SADDR = 0101 0110b SADEN = 1111 1100b (SADDR | SADEN)=1111 111Xb SADEN = 1111 1010b Given = 1111 1X11b, SADEN = 1111 1001b Given = 1111 1X11b, SADEN = 1111 1101b Given = 1111 1111b, AT89C5132 115 ...
Page 116
... Depending on the selected mode and whether the framing error detection is enabled or not, RI flag is set during the stop bit or during the ninth bit as detailed in Figure 18-17. Figure 18-16. Serial I/O Interrupt System Figure 18-17. Interrupt Waveforms SMOD0 = X SMOD0 = 1 SMOD0 = 0 SMOD0 = 1 SMOD0 = 1 18.8 Registers Table 91. SCON Register AT89C5132 116 SCON SCON.1 RXD Start Bit ...
Page 117
... Set by the receiver after the stop bit of a frame has been received. Must be cleared by software SD6 SD5 SD4 Bit Mnemonic Description Serial Data Byte SD7:0 Read the last data received by the Serial I/O Port. Write the data to be transmitted by the Serial I/O Port. AT89C5132 TB8 RB8 SD3 SD2 SD1 0 RI ...
Page 118
... SADEN (S:B9h) – Slave Individual Address Mask Byte Register 7 SAE7 Bit Number Reset Value = 0000 0000b Table 95. BDRCON Register BDRCON (S:92h) – Baud Rate Generator Control Register 7 - Bit Number 7 AT89C5132 118 SAD6 SAD5 SAD4 Bit Mnemonic Description SAD7:0 Slave Individual Address SAE6 ...
Page 119
... Reset Value = XXX0 0000b Table 96. BRL Register BRL (S:91h) – Baud Rate Generator Reload Register 7 BRL7 Bit Number 7-0 Reset Value = 0000 0000b 4173E–USB–09/ BRL6 BRL5 BRL4 Bit Mnemonic Description BRL7:0 Baud Rate Reload Value. AT89C5132 BRL3 BRL2 BRL1 0 BRL0 119 ...
Page 120
... Each slave peripheral is selected by one Slave Select pin (SS). If there is only one slave, it may be continuously selected with SS tied to a low level. Otherwise, the AT89C5132 may select each device by software through port pins (Pn.x). Special care should be taken not to select two slaves at the same time to avoid bus conflicts ...
Page 121
... MISO pin. The byte is transmitted most significant bit (MSB) first. The end of transfer is signalled by SPIF being set. In case of the AT89C5132 is the only master on the bus, it can be useful not to use SS pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. ...
Page 122
... In case of the AT89C5132 is the only slave on the bus, it can be useful not to use SS pin and get it back to I/O functionality. This is achieved by setting SSDIS bit in SPCON. This bit has no effect when CPHA is cleared (see Section "SS Management", page 123). Figure 19-4. SPI Slave Mode Block Diagram MISO/P4 ...
Page 123
... AT89C5132 captures data from the SI line while the selected slave captures data from the SO line. For simplicity, the following figures depict the SPI waveforms in idealized form and do not pro- vide precise timing information. For timing parameters refer to the Section “AC Characteristics”. ...
Page 124
... SPCON. The SPI interrupt is enabled by setting ESPI bit in IEN1 register. This assumes interrupts are globally enabled by setting EA bit in IEN0 register. Figure 19-8. SPI Interrupt System 19.3 Configuration The SPI configuration is made through SPCON. AT89C5132 124 Byte 1 SI/SO SS (CPHA = 0) SS (CPHA = 1) SPIF SPSTA ...
Page 125
... SPIF flag is cleared when reading SPDAT (SPSTA has been read before by the “end of transfer” check). This policy provides the fastest effective transmission and is well adapted when communicating at high speed with other Microcontrollers. However, the procedure may then be interrupted at any time by higher priority tasks. 4173E–USB–09/07 AT89C5132 125 ...
Page 126
... The transfer format depends on the slave peripheral. • SS may be deasserted between transfers depending also on the slave peripheral. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT. AT89C5132 126 SPIE = 0 MSTR = 1 Select Format Enable SPI ...
Page 127
... Select Format Program CPOL & CPHA Enable Interrupt ESPI =1 Enable SPI SPEN = 1 Select Slave Pn Start Transfer Write Data in SPDAT AT89C5132 SPI Interrupt Service Routine Read Status Read SPSTA Get Data Received Read SPDAT Start New Transfer Write Data in SPDAT Last Transfer? Deselect Slave Pn ...
Page 128
... Figure 19-10 shows the initialization phase and the transfer phase flows using the interrupt policy. The transfer format depends on the master controller. Reading SPSTA at the beginning of the ISR is mandatory for clearing the SPIF flag. Clear is effective when reading SPDAT. AT89C5132 128 SPI Initialization Polling Policy Disable interrupt ...
Page 129
... SPI Clock Phase Bit CPHA Set to have the data sampled when the clock returns to idle state (see CPOL). Clear to have the data sampled when the clock leaves the idle state (see CPOL). AT89C5132 SPI Interrupt Service Routine Get Status Read SPSTA ...
Page 130
... Reset Value = 00000 0000b Table 100. SPDAT Register SPDAT (S:C5h) – Synchronous Serial Data Register 7 SPD7 Bit Number Reset Value = XXXX XXXXb AT89C5132 130 Bit Mnemonic Description SPI Rate Bits 0 and 1 SPR1:0 Refer to Table 97 for bit rate description. 1. When the SPI is disabled, SCK outputs high level. ...
Page 131
... Various communication configurations can be designed using this bus. Figure 20-1 shows a typical TWI bus configuration using the AT89C5132 in master and slave modes. All the devices connected to the bus can be master and slave. Figure 20-1. Typical TWI Bus Configuration Master/Slave 20 ...
Page 132
... The bit rate can be selected from seven predefined bit rates or from a programmable bit rate generator using the SSCR2, SSCR1, and SSCR0 control bits in SSCON (see Table 26). The predefined bit rates are derived from the peripheral clock (F block as detailed in Section "Oscillator", page 12, while bit rate generator is based on timer 1 overflow output. AT89C5132 132 R/W ACK direction ...
Page 133
... These bit rates are outside of the low speed standard specification limited to 100 kHz but can be used with high speed TWI components limited to 400 kHz. SSPE SSSTA SSSTO AT89C5132 MHz F Divided By PER PER 78.125 89.3 (1) 104.2 ...
Page 134
... SSSTA. This status code is used to vector to an interrupt service routine, and the appropriate action to be taken for each of these status code is detailed in Table 24. The slave transmitter mode may also be entered if arbitration is lost while the controller is in the master mode (see state B0h). AT89C5132 134 SSA5 SSA4 ...
Page 135
... The TWI controller interfaces to the external TWI bus via 2 port 1 pins: P1.6/SCL (serial clock line) and P1.7/SDA (serial data line). To avoid low level asserting and conflict on these lines when the TWI controller is enabled, the output latches of P1.6 and P1.7 must be set to logic 1. AT89C5132 135 ...
Page 136
... Not acknowledge received after the slave address Not acknowledge received after a data Byte Arbitration lost in slave address or data Byte Arbitration lost and addressed as slave From master to slave From slave to master AT89C5132 136 MT SLA W A Data 18h A P 20h ...
Page 137
... Other master A continues 68h 78h B0h Any number of data Bytes and their associated Data A acknowledge bits This number (contained in SSSTA) corresponds nnh to a defined state of the TWI bus AT89C5132 Data A P 58h S SLA R 10h W MT Other master A continues 38h ...
Page 138
... Arbitration lost as master and addressed as slave Reception of the general call address and one or more data Bytes Last data Byte received is not acknowledged Arbitration lost as master and addressed as slave by general call From master to slave From slave to master AT89C5132 138 S SLA W A Data 60h A 68h ...
Page 139
... From slave to master 4173E–USB–09/07 S SLA R A Data A8h A B0h Any number of data Bytes and their associated Data A acknowledge bits This number (contained in SSSTA) corresponds nnh to a defined state of the TWI bus AT89C5132 A Data B8h C0h A All 1’ C8h 139 ...
Page 140
... No SSDAT action Write data Byte No SSDAT action Data Byte has been 30h transmitted; NOT ACK No SSDAT action has been received No SSDAT action No SSDAT action Arbitration lost in 38h SLA+W or data Bytes No SSDAT action AT89C5132 140 Application Software Response To SSCON SSSTA SSSTO SSI SSAA ...
Page 141
... AT89C5132 Next Action Taken by TWI Hardware X SLA+R will be transmitted. SLA+R will be transmitted. X SLA+W will be transmitted. X Logic will switch to master transmitter mode. TWI bus will be released and not addressed slave X mode will be entered. A START condition will be transmitted when the bus X becomes free. ...
Page 142
... NOT ACK has been Read data Byte returned Read data Byte No SSDAT action No SSDAT action A STOP condition or repeated START A0h condition has been received while still No SSDAT action addressed as slave No SSDAT action AT89C5132 142 Application Software Response To SSCON SSSTA SSSTO SSI SSAA ...
Page 143
... AT89C5132 Next Action Taken by TWI Hardware 0 Data Byte will be received and NOT ACK will be returned. 1 Data Byte will be received and ACK will be returned. 0 Data Byte will be received and NOT ACK will be returned. 1 Data Byte will be received and ACK will be returned. 0 Data Byte will be received and NOT ACK will be returned ...
Page 144
... Status Code Status of the TWI Bus SSSTA and TWI Hardware To/From SSDAT No relevant state F8h information available; No SSDAT action SSI = 0 Bus error due to an 00h illegal START or STOP No SSDAT action condition AT89C5132 144 Application Software Response To SSCON SSSTA SSSTO SSI SSAA ...
Page 145
... Clear to isolate slave from the bus after last data Byte transmission. Set to enable slave mode. Synchronous Serial Control Rate Bit 1 SSCR1 Refer to Table 19 for rate description. Synchronous Serial Control Rate Bit 0 SSCR0 Refer to Table 19 for rate description SSC3 SSC2 SSC1 AT89C5132 SSI SSAA SSCR1 SSC0 ...
Page 146
... Reset Value = 1111 1111b Table 29. SSADR Register SSADR (S:96h) – Synchronous Serial Address Register 7 SSA7 Bit Number 7:1 0 Reset Value = 1111 1110b AT89C5132 146 Bit Mnemonic Description Synchronous Serial Status Code Bits SSC4:0 Refer to Table 20 to Table 20-6 for status description. 0 Always 0 ...
Page 147
... Analog to Digital Converter The AT89C5132 implement a 2-channel 10-bit (8 true bits) analog to digital converter (ADC). First channel of this ADC can be used for battery monitoring while the second one can be used for voice sampling at 8 kHz. 21.1 Description The A/D converter interfaces with the C51 core through four special function registers: ADCON, ...
Page 148
... The 10-bit precision conversion is achieved by stopping the CPU core activity during conversion for limiting the digital noise induced by the core. This mode called the Pseudo-Idle mode enabled by setting the ADIDL bit in ADCON register Section "Conversion Launching", page 149), the CPU core is stopped until the end of the con- AT89C5132 148 CLK T ...
Page 149
... If some interrupts occur during the Pseudo-Idle mode, they will be delayed and processed, according to their priority after the end of the conversion. 3. Concurrently with ADSST bit. Configuration Program ADC Clock ADCD4:0 = xxxxxb Wait Setup Time Conversion Start Start Conversion AT89C5132 ) before launching any conversion. SETUP ADC Enable ADC ADIDL = x ADEN = 1 ADC Select Channel ...
Page 150
... Reset Value = 0000 0000b Table 32. ADCLK Register ADCLK (S:F2h) – ADC Clock Divider Register 7 - Bit Number Reset Value = 0000 0000b AT89C5132 150 ADIDL ADEN ADEOC Bit Mnemonic Description Reserved - The value read from this bit is always 0. Do not set this bit. ...
Page 151
... ADAT9:2 8 Most Significant Bits of the 10-bit ADC data Bit Mnemonic Description Reserved - The value read from these bits is always 0. Do not set these bits. ADC Data ADAT1:0 2 Least Significant Bits of the 10-bit ADC data. AT89C5132 ADAT5 ADAT4 ADAT3 ADAT1 0 ADAT2 0 ADAT0 ...
Page 152
... Keyboard Interface The AT89C5132 implements a keyboard interface allowing the connection matrix key- board based on 4 inputs with programmable interrupt capability on both high or low level. These inputs are available as alternate function of P1.3:0 and allow exit from idle and power down modes. 22.1 ...
Page 153
... Clear to disable exit of power down mode by the keyboard interrupt. Reserved - The values read from these Bits are always 0. Do not set these Bits. Keyboard Input Interrupt Flag KINF3:0 Set by hardware when the respective KIN3:0 input detects a programmed level. Cleared when reading KBSTA. AT89C5132 KINM3 KINM2 KINM1 3 ...
Page 154
... OH2 MDAT, MCLK, SCLK, DCLK, DSEL, DOUT, D+, D-) Logical 0 Input Current (P1, P2, P3 and P5) AT89C5132 154 *NOTICE: Stressing the device beyond the “Absolute Maxi- mum Ratings” may cause permanent damage. -0.3 to +4.0V These are stress ratings only. Operation beyond the “operating conditions” is not recommended and extended exposure beyond the “ ...
Page 155
... Flash retention is guaranteed with the same formula for V 3. See Table 154 for typical consumption in player mode. Test Condition, Active Mode DD VDD RST (NC) X2 Clock Signal X1 VSS PVSS UVSS AVSS VSS All other pins are unconnected AT89C5132 (1) Max Units 10 0.45< V µA -650 µA Vin = 2.0 V 200 kΩ 25° ...
Page 156
... A-to-D Converter Table 104. A-to-D Converter DC Characteristics V = 2 Symbol REF R REF C IA AT89C5132 156 Test Condition, Idle Mode DL RST VSS (NC) X2 Clock Signal X1 VSS PVSS UVSS AVSS VSS All other pins are unconnected Test Condition, Power-Down Mode PD RST VSS (NC) ...
Page 157
... X1 and X2 to ground in special cases (max 10 pF). X1 and X2 may not be used to drive other circuits. = -40 to +85°C A Parameter V Internal Capacitance ( Internal Capacitance ( Equivalent Load Capacitance (X1 - X2) Drive Level Crystal Frequency Crystal Series Resistance Crystal Shunt Capacitance FILT AT89C5132 Min Typ Max VSS VSS Unit µ ...
Page 158
... USB R FS 23.2.7 In-system Programming 23.2.7.1 Schematic Figure 23-7. ISP Pull-down Connection 23.2.7.2 Parameters Table 107. ISP Pull-Down Characteristics 3. Symbol R ISP AT89C5132 158 = -40 to +85°C A Parameter Filter Resistor Filter Capacitance 1 Filter Capacitance 2 To Power VBUS Supply D+ D- GND VSS = -40 to +85°C A ...
Page 159
... CLCL RD high to ALE High T CLCL Address Valid to Valid Data In Address Valid to RD Low 4·T CLCL RD Low to Valid Data RD Low to Address Float Data Hold After RD High Instruction Float After RD High AT89C5132 Conditions Variable Clock Variable Clock Standard Mode X2 Mode Max Min ...
Page 160
... LLAX T LLWL T WLWH T WHLH T AVWL T QVWH T WHQX 23.3.1.3 Waveforms Figure 23-8. External 8-bit Bus Cycle – Data Read Waveforms AT89C5132 160 = -40° to +85°C A Variable Clock Standard Mode Parameter Min Clock Period 50 ALE Pulse Width 2·T -15 CLCL Address Valid to ALE Low T ...
Page 161
... Test conditions: capacitive load on all pins = 50 pF. 4173E–USB–09/07 ALE T LHLL T LLWL WR T AVWL T T AVLL LLAX P0 A7:0 P2 Signals A Address D Data In L ALE Q Data Out AT89C5132 T T WLWH WHLH T T QVWH WHQX D7:0 Data Out A15:8 Conditions High Low Valid No Longer Valid Floating 161 ...
Page 162
... T CLCL T LHLL T AVLL T LLAX T LLWL T WLWH T WHLH T AVWL T QVWH T WHQX AT89C5132 162 = -40° to +85°C A Variable Clock Standard Mode Parameter Min Clock Period 50 ALE Pulse Width 2·T CLCL Address Valid to ALE Low T -20 CLCL Address hold after ALE Low T -20 CLCL ALE Low to RD Low 3· ...
Page 163
... D15:8 is written in DAT16H SFR. ALE T LHLL T LLWL WR T AVWL T T AVLL LLAX P0 A7:0 P2 A15:8 D15:8 is the content of DAT16H SFR. Signals C Clock I Data In O Data Out AT89C5132 T T RLRH RHLH T RLDV T RHDZ T RHDX D7:0 Data In D15:81 Data WHLH WLWH T T QVWH WHQX D7:0 Data Out ...
Page 164
... CLOX CHOX T ILIH T IHIL T OLOH T OHOL Notes: AT89C5132 164 = -40° to +85°C A Parameter Clock Period Clock High Time Clock Low Time SS Low to Clock edge Input Data Valid to Clock Edge Input Data Hold after Clock Edge Output Data Valid after Clock Edge ...
Page 165
... IVCL CLIX MSB IN BIT 6 T CHCH T T CHCX CLCX T T IVCH CHIX T T IVCL CLIX MSB IN BIT 6 T CLOV T CHOV MSB OUT BIT 6 AT89C5132 T CLSH T T SHSL CHSH T CLCH T CHCL T CLOX T T SHOX CHOX 1 LSB IN T CLCH T CHCL LSB IN T CLOX ...
Page 166
... SCK (SSCPOL = 0) (output) SCK (SSCPOL = 1) (output) SI (input) SO Port Data (output) Note handled by software using general purpose port pin. 23.3.4 Two-wire Interface 23.3.4.1 Timings Table 36. TWI Interface AC Timing AT89C5132 166 T SLCH T T SLCL CHCH T T CHCX CLCX T CHOV T SLOV T CLOV SLAVE MSB OUT ...
Page 167
... Maxi- CLCL Repeated START condition T ;STA STOP condition su T ;STO su T DAT3 su 0.7 V 0.3 V Tsu;DAT 2 DAT AT89C5132 OUTPUT Min Max (4) (1) 4.0 µs (4) (1) 4.7 µs (4) (1) 4.0 µs (2) - (3) 0.3 µs (4) 20· CLCL RD (1) 1 µ ...
Page 168
... CLCX T CLCH T CHCL T DVCH T CHDX T CHOX T OVCH 23.3.5.3 Waveforms Figure 23-17. MMC Input Output Waveforms AT89C5132 168 Signals C Clock D Data In O Data Out = -40 to +85°C, CL ≤ 100pF (10 cards) A Parameter Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time ...
Page 169
... CL ≤ 30pF A Parameter Clock Period Clock High Time Clock Low Time Clock Rise Time Clock Fall Time Clock Low to Select Valid Clock Low to Data Valid 32-bit format with kHz. DCLK DSEL Right T CLOV DDAT AT89C5132 Conditions Min Max (1) 325 ...
Page 170
... Characteristics Table 37. Analog to Digital Converter AC Characteristics V = 2 Symbol T CLCL T EHSH T SHSL DLe ILe OSe Ge Notes: AT89C5132 170 Signals C Clock E Enable (ADEN bit) Start Conversion S (ADSST bit) = -40 to +85°C A Parameter Clock Period Start-up Time Conversion Time Differential non- (1)(2) linearity error ...
Page 171
... OSe 4173E–USB–09/07 T CLCL T SHSL Ideal Transfer Curve Center of a Step Integral Non-linearity (ILe) Differential Non-linearity (DLe) 1 LSB (Ideal 1018 1019 1020 1021 1022 1023 1024 AT89C5132 Offset Gain Error Error OSe Ge Example of an Actual Transfer Curve AVIN (LSBideal) 171 ...
Page 172
... Figure 23-21. Flash Memory – ISP Waveforms Note: Figure 23-22. Flash Memory – Internal Busy Waveforms 23.3.9 External Clock Drive and Logic Level References 23.3.9.1 Definition of Symbols Table 123. External Clock Timing Symbol Definitions AT89C5132 172 Signals S ISP R RST B FBUSY flag = -40° ...
Page 173
... IH1 CHCL INPUTS -0.5V for a logic 1 and 0.45V for a logic 0. DD min for a logic 1 and 0.1V LOAD Timing Reference Points V - 0.1V LOAD /V level occurs with AT89C5132 Min CLCH CHCX T CLCX T CLCL OUTPUTS V min IH V max IL max for a logic 0. 0. ±20 mA. ...
Page 174
... Ordering Information (1) Possible Order Entries Memory Size Part Number (Bytes) AT89C5132-ROTIL 64K Flash AT89C5132-ROTUL 64K Flash Note: 1. PLCC84 package only available for development board. AT89C5132 174 Max Temperature Supply Frequency Voltage Range (MHz) 3V Industrial 40 Industrial & Green Product Package Packing Marking ...
Page 175
... Package Information 25.1 TQFP80 4173E–USB–09/07 AT89C5132 175 ...
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... PLCC84 AT89C5132 176 4173E–USB–09/07 ...
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... Datasheet Revision History for AT89C5132 26.1 Changes from 4173A-08/02 to 4173B-03/04 1. Suppression of ROM product version. 2. Suppression of TQFP64 package. 26.2 Changes from 4173B-03/04 - 4173C - 07/04 1. Add USB connection schematic in USB section. 2. Add USB termination characteristics in DC Characteristics section. 3. Page access mode clarification in Data Memory section. ...
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... Clock Controller ..................................................................................... 12 7 Program/Code Memory ......................................................................... 17 8 Data Memory .......................................................................................... 22 9 Special Function Registers ................................................................... 29 10 Interrupt System .................................................................................... 34 11 Power Management ............................................................................... 44 AT89C5132 i 4.1 Signals ......................................................................................................................4 4.2 Internal Pin Structure ..............................................................................................10 6.1 Oscillator ................................................................................................................12 6.2 X2 Feature ..............................................................................................................12 6.3 PLL .........................................................................................................................13 6.4 Registers ................................................................................................................14 7.1 Flash Memory Architecture ....................................................................................17 7.2 Hardware Security System .....................................................................................18 7 ...
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... Interrupt Request ..................................................................................................63 14.6 Voice or Sound Playing ........................................................................................63 14.7 Registers ..............................................................................................................64 15.1 Description ...........................................................................................................68 15.2 USB Interrupt System ...........................................................................................70 15.3 Registers ..............................................................................................................72 16.1 Card Concept .......................................................................................................82 16.2 Bus Concept .........................................................................................................82 16.3 Description ...........................................................................................................87 16.4 Clock Generator ...................................................................................................88 16.5 Command Line Controller ....................................................................................88 16.6 Data Line Controller .............................................................................................90 16.7 Interrupt ................................................................................................................96 16.8 Registers ..............................................................................................................97 AT89C5132 ii ...
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... Two-wire Interface (TWI) Controller ................................................... 131 21 Analog to Digital Converter ................................................................ 147 22 Keyboard Interface .............................................................................. 152 23 Electrical Characteristics .................................................................... 154 24 Ordering Information ........................................................................... 174 25 Package Information ............................................................................ 175 AT89C5132 iii 17.1 Description .........................................................................................................104 17.2 Registers ............................................................................................................106 18.1 Mode Selection ...................................................................................................107 18.2 Baud Rate Generator .........................................................................................107 18.3 Synchronous Mode (Mode 0) .............................................................................108 18 ...
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... Datasheet Revision History for AT89C5132 ...................................... 177 4173E–USB–09/07 25.2 PLCC84 ..............................................................................................................176 26.1 Changes from 4173A-08/02 to 4173B-03/04 ......................................................177 26.2 Changes from 4173B-03/04 - 4173C - 07/04 .....................................................177 26.3 Changes from 4173C-07/04 - 4173D - 01/05 .....................................................177 26.4 Changes from to 4317D - 01/05 to 4173E - 09/07 .............................................177 AT89C5132 ...
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... Atmel does not make any commitment to update the information contained herein. Unless specifically providedot- herwise, Atmel products are not suitable for, and shall not be used in, automotive applications. Atmel’sAtmel’s products are not intended, authorized, or warranted for use as components in applications intended to support or sustain life. © ...