AT89C5132-ROTUL Atmel, AT89C5132-ROTUL Datasheet - Page 96
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AT89C5132-ROTUL
Manufacturer Part Number
AT89C5132-ROTUL
Description
IC 8051 MCU FLASH 64K USB 80TQFP
Manufacturer
Atmel
Series
AT89C513xr
Specifications of AT89C5132-ROTUL
Core Processor
C52X2
Core Size
8-Bit
Speed
20MHz
Connectivity
IDE/ATAPI, I²C, MMC, PCM, SPI, UART/USART, USB
Peripherals
I²S, POR, WDT
Number Of I /o
44
Program Memory Size
64KB (64K x 8)
Program Memory Type
FLASH
Eeprom Size
4K x 8
Ram Size
2.25K x 8
Voltage - Supply (vcc/vdd)
2.7 V ~ 3.3 V
Data Converters
A/D 2x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
80-TQFP, 80-VQFP
Cpu Family
89C
Device Core
8051
Device Core Size
8b
Frequency (max)
40MHz
Interface Type
IDE/SPI/UART/USB
Total Internal Ram Size
2.25KB
# I/os (max)
44
Number Of Timers - General Purpose
2
Operating Supply Voltage (typ)
3V
Operating Supply Voltage (max)
3.3V
Operating Supply Voltage (min)
2.7V
On-chip Adc
2-chx10-bit
Instruction Set Architecture
CISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
80
Package Type
TQFP
Package
80TQFP
Family Name
89C
Maximum Speed
40 MHz
Operating Supply Voltage
3 V
Data Bus Width
8 Bit
Number Of Programmable I/os
44
Number Of Timers
2
Maximum Clock Frequency
20 MHz
Data Ram Size
2304 B
Mounting Style
SMD/SMT
A/d Bit Size
10 bit
A/d Channels Available
2
Height
1.45 mm
Length
14.1 mm
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Supply Voltage (max)
3.3 V
Supply Voltage (min)
2.7 V
Width
14.1 mm
For Use With
AT89OCD-01 - USB EMULATOR FOR AT8XC51 MCU
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Figure 16-19. Data Block Reception Flows
16.6.5
16.7
16.7.1
96
Interrupt
AT89C5132
Flow Control
Description
read 8 data from MMDAT
a. Polling Mode
Start Transmission
F1EI or F2EI = 1?
FIFO Reading
No More Data
Data Block
To Receive?
Reception
DATEN = 1
DATEN = 0
FIFO Full?
To allow transfer at high speed without taking care of CPU oscillator frequency, the FLOWC bit
in MMCON2 allows control of the data flow in both transmission and reception.
During transmission, setting the FLOWC bit has the following effects:
•
•
During reception, setting the FLOWC bit has the following effects:
•
•
As soon as the clock is stopped, the MMC bus is frozen and remains in its state until the clock is
restored by writing or reading data in MMDAT.
As shown in Figure 16-20, the MMC controller implements eight interrupt sources reported in
MCBI, EORI, EOCI, EOFI, F2FI, F1FI, and F2EI flags in MMCINT register. These flags were
detailed in the previous sections.
All of these sources are maskable separately using MCBM, EORM, EOCM, EOFM, F2FM,
F1FM, and F2EM mask bits, respectively, in MMMSK register.
MMCLK is stopped when both FIFOs become empty: F1EI and F2EI set.
MMCLK is restarted when one of the FIFOs becomes full: F1EI or F2EI cleared.
MMCLK is stopped when both FIFOs become full: F1FI and F2FI set.
MMCLK is restarted when one of the FIFOs becomes empty: F1FI or F2FI cleared.
Unmask FIFOs Full
Start Transmission
Initialization
Data Block
DATEN = 1
DATEN = 0
F1FM = 0
F2FM = 0
read 8 data from MMDAT
b. Interrupt Mode
F1EI or F2EI = 1?
Reception ISR
Mask FIFOs Full
FIFO Reading
No More Data
Data Block
To Receive?
FIFO Full?
F1FM = 1
F2FM = 1
4173E–USB–09/07