DSPIC30F6012A-30I/PF Microchip Technology, DSPIC30F6012A-30I/PF Datasheet - Page 63

• Manufacturer Part Number: DSPIC30F6012A-30I/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

TABLE 7-9:
TRISG
PORTG
LATG
Legend:
Note
Name
SFR
1:
Addr.
02E4
02E6
02E8
Refer to “dsPIC30F Family Reference Manual” (DS70046) for descriptions of register bit fields.
u = uninitialized bit; — = unimplemented bit, read as ‘0’
TRISG15 TRISG14 TRISG13 TRISG12
LATG15
Bit 15
RG15
PORTG REGISTER MAP FOR dsPIC30F6011A/6012A/6013A/6014A
LATG14
Bit 14
RG14
LATG13
Bit 13
RG13
LATG12
Bit 12
RG12
Bit 11 Bit 10
—
—
—
—
—
—
TRISG9
LATG9
Bit 9
RG9
TRISG8
LATG8
Bit 8
RG8
TRISG7
LATG7
Bit 7
RG7
TRISG6
LATG6
Bit 6
RG6
(1)
Bit 5
—
—
—
Bit 4
—
—
—
TRISG3
LATG3
Bit 3
RG3
TRISG2
LATG2
Bit 2
RG2
TRISG1
LATG1
Bit 1
RG1
TRISG0
LATG0
Bit 0
RG0
1111 0011 1100 1111
0000 0000 0000 0000
0000 0000 0000 0000
Reset State