DSPIC30F6012A-30I/PF Microchip Technology, DSPIC30F6012A-30I/PF Datasheet - Page 229

• Manufacturer Part Number: DSPIC30F6012A-30I/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

I/O Ports .............................................................................. 59
I
I
I
I
I
I
Idle Current (I
In-Circuit Debugger (ICD 2) .............................................. 162
In-Circuit Serial Programming (ICSP) ......................... 53, 145
Initialization Condition for RCON Register Case 1 ........... 159
Initialization Condition for RCON Register Case 2 ........... 159
Input Capture (CAPX) Timing Characteristics .................. 196
Input Capture Module ......................................................... 85
Input Capture Operation During Sleep and Idle Modes ...... 86
Input Capture Timing Requirements ................................. 196
Input Change Notification Module ....................................... 64
Instruction Addressing Modes............................................. 41
© 2008 Microchip Technology Inc.
2
2
2
2
2
2
C 10-bit Slave Mode Operation ........................................ 99
C 7-bit Slave Mode Operation .......................................... 99
C Master Mode Operation .............................................. 101
C Master Mode Support ................................................. 101
C Module .......................................................................... 97
S Mode Operation .......................................................... 133
Input .......................................................................... 183
Output ....................................................................... 183
Parallel (PIO) .............................................................. 59
Reception.................................................................. 100
Transmission............................................................... 99
Reception.................................................................... 99
Transmission............................................................... 99
Baud Rate Generator................................................ 102
Clock Arbitration........................................................ 102
Multi-Master Communication, Bus Collision and Bus Ar-
Reception.................................................................. 101
Transmission............................................................. 101
Addresses ................................................................... 99
Bus Data Timing Characteristics
Bus Data Timing Requirements
Bus Start/Stop Bits Timing Characteristics
General Call Address Support .................................. 101
Interrupts................................................................... 100
IPMI Support ............................................................. 101
Operating Function Description .................................. 97
Operation During CPU Sleep and Idle Modes .......... 102
Pin Configuration ........................................................ 97
Programmer’s Model................................................... 97
Register Map............................................................. 103
Registers..................................................................... 97
Slope Control ............................................................ 101
Software Controlled Clock Stretching
Various Modes ............................................................ 97
Data Justification....................................................... 133
Frame and Data Word Length Selection................... 133
Interrupts..................................................................... 86
Register Map............................................................... 87
CPU Idle Mode............................................................ 86
CPU Sleep Mode ........................................................ 86
Register Map for dsPIC30F6011A/6012 A (Bits 7-0) .. 64
Register Map for dsPIC30F6011A/6012A (Bits 15-8) . 64
Register Map for dsPIC30F6013A/6014A (Bits 15-8) . 64
Register Map for dsPIC30F6013A/6014A (Bits 7-0) ... 64
File Register Instructions ............................................ 41
(STREN = 1) ............................................................ 100
bitration ............................................................. 102
Master Mode ..................................................... 206
Slave Mode ....................................................... 208
Master Mode ..................................................... 207
Slave Mode ....................................................... 209
Master Mode ..................................................... 206
Slave Mode ....................................................... 208
IDLE
) ............................................................ 180
dsPIC30F6011A/6012A/6013A/6014A
Instruction Set
Internet Address ............................................................... 233
Interrupt Controller
Interrupt Priority .................................................................. 48
Interrupt Sequence ............................................................. 50
Interrupts ............................................................................ 47
L
Load Conditions................................................................ 186
Low Voltage Detect (LVD) ................................................ 160
Low-Voltage Detect Characteristics.................................. 183
LVDL Characteristics ........................................................ 184
M
Memory Organization3, 11, 17, 27, 41, 47, 53, 59, 65, 71, 75,
Microchip Internet Web Site.............................................. 233
Modes of Operation
Module ................................................................................ 97
Modulo Addressing ............................................................. 42
MPLAB ASM30 Assembler, Linker, Librarian ................... 174
MPLAB ICD 2 In-Circuit Debugger ................................... 175
MPLAB ICE 2000 High-Performance Universal
In-Circuit Emulator ............................................................ 175
MPLAB Integrated Development Environment
Software ........................................................................... 173
MPLAB PM3 Device Programmer .................................... 175
MPLAB REAL ICE In-Circuit Emulator System ................ 175
MPLINK Object Linker/MPLIB Object Librarian ................ 174
N
NVM
O
OC/PWM Module Timing Characteristics ......................... 197
Operating Current (I
Oscillator
Oscillator Configurations................................................... 148
Fundamental Modes Supported ................................. 41
MAC Instructions ........................................................ 42
MCU Instructions ........................................................ 41
Move and Accumulator Instructions ........................... 42
Other Instructions ....................................................... 42
Overview................................................................... 168
Summary .................................................................. 165
Register Map .............................................................. 52
Interrupt Stack Frame................................................. 51
81, 85, 89, 93, 97, 105, 113, 125, 135, 165
Core Register Map ..................................................... 39
Disable...................................................................... 115
Initialization............................................................... 115
Listen All Messages.................................................. 115
Listen Only................................................................ 115
Loopback .................................................................. 115
Normal Operation ..................................................... 115
Applicability................................................................. 44
Operation Example..................................................... 43
Start and End Address ............................................... 43
W Address Register Selection.................................... 43
Register Map .............................................................. 57
Control Registers...................................................... 151
Operating Modes (Table).......................................... 146
System Overview...................................................... 145
Fail-Safe Clock Monitor ............................................ 150
Fast RC (FRC).......................................................... 149
Initial Clock Source Selection ................................... 148
Low-Power RC (LPRC) ............................................ 150
DD
) .................................................... 179
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