DSPIC30F6012A-30I/PF Microchip Technology, DSPIC30F6012A-30I/PF Datasheet - Page 49

• Manufacturer Part Number: DSPIC30F6012A-30I/PF
• Description: IC DSPIC MCU/DSP 144K 64TQFP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 30Fr

Specifications of DSPIC30F6012A-30I/PF

• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 30 MIPs
• Connectivity: CAN, I²C, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, I²S, LVD, POR, PWM, WDT
• Number Of I /o: 52
• Program Memory Size: 144KB (48K x 24)
• Program Memory Type: FLASH
• Eeprom Size: 4K x 8
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 2.5 V ~ 5.5 V
• Data Converters: A/D 16x12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Core Frequency: 40MHz
• Core Supply Voltage: 5.5V
• Embedded Interface Type: CAN, I2C, SPI, UART
• No. Of I/o's: 52
• Flash Memory Size: 144KB
• Supply Voltage Range: 2.5V To 5.5V
• Package: 64TQFP
• Device Core: dsPIC
• Family Name: dsPIC30
• Maximum Speed: 30 MHz
• Operating Supply Voltage: 3.3|5 V
• Data Bus Width: 16 Bit
• Number Of Programmable I/os: 52
• Interface Type: CAN/I2C/SPI/UART
• On-chip Adc: 16-chx12-bit
• Number Of Timers: 5
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT64PT4 - SOCKET TRAN ICE 64MQFP/TQFPAC164313 - MODULE SKT FOR PM3 64PFAC30F002 - MODULE SOCKET DSPIC30F 64TQFPDV164005 - KIT ICD2 SIMPLE SUIT W/USB CABLE
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant

5.2
A Reset is not a true exception, because the interrupt
controller is not involved in the Reset process. The
processor initializes its registers in response to a Reset
which forces the PC to zero. The processor then begins
program execution at location 0x000000. A GOTO
instruction is stored in the first program memory
location immediately followed by the address target for
the GOTO instruction. The processor executes the GOTO
to the specified address and then begins operation at
the specified target (start) address.
5.2.1
In addition to external Reset and Power-on Reset
(POR), there are 6 sources of error conditions which
‘trap’ to the Reset vector.
• Watchdog Time-out:
• Uninitialized W Register Trap:
• Illegal Instruction Trap:
• Brown-out Reset (BOR):
• Trap Lockout:
• Software Reset Instruction
5.3
Traps can be considered as non-maskable interrupts
indicating a software or hardware error, which adhere
to a predefined priority, as shown in Table 5-1. They are
intended to provide the user a means to correct
erroneous operation during debug and when operating
within the application.
© 2008 Microchip Technology Inc.
The watchdog has timed out, indicating that the
processor is no longer executing the correct flow
of code.
An attempt to use an uninitialized W register as
an address pointer will cause a Reset.
Attempted execution of any unused opcodes will
result in an illegal instruction trap. Note that a
fetch of an illegal instruction does not result in an
illegal instruction trap if that instruction is flushed
prior to execution due to a flow change.
A momentary dip in the power supply to the
device has been detected which may result in
malfunction.
Occurrence of multiple trap conditions
simultaneously will cause a Reset.
Note:
Reset Sequence
Traps
RESET SOURCES
If the user does not intend to take
corrective action in the event of a trap
error condition, these vectors must be
loaded with the address of a default
handler that simply contains the RESET
instruction. If, on the other hand, one of
the vectors containing an invalid address
is called, an address error trap is
generated.
dsPIC30F6011A/6012A/6013A/6014A
Note that many of these trap conditions can only be
detected
questionable instruction is allowed to complete prior to
trap exception processing. If the user chooses to
recover from the error, the result of the erroneous
action that caused the trap may have to be corrected.
There are 8 fixed priority levels for traps: level 8 through
level 15, which implies that the IPL3 is always set
during processing of a trap.
If the user is not currently executing a trap, and he sets
the IPL<3:0> bits to a value of ‘0111’ (level 7), then all
interrupts are disabled but traps can still be processed.
5.3.1
The following traps are provided with increasing
priority. However, since all traps can be nested, priority
has little effect.
Math Error Trap:
The math error trap executes under the following four
circumstances:
• Should an attempt be made to divide by zero, the
• If enabled, a math error trap will be taken when an
• If enabled, a math error trap will be taken when an
• If the shift amount specified in a shift instruction is
Address Error Trap:
This trap is initiated when any of the following
circumstances occurs:
• A misaligned data word access is attempted.
• A data fetch from and unimplemented data mem-
• A data fetch from an unimplemented program
• An instruction fetch from vector space is
• Execution of a “BRA #literal” instruction or a
• Executing instructions after modifying the PC to
divide operation will be aborted on a cycle
boundary and the trap taken.
arithmetic operation on either accumulator A or B
causes an overflow from bit 31 and the
accumulator guard bits are not utilized.
arithmetic operation on either accumulator A or B
causes a catastrophic overflow from bit 39 and all
saturation is disabled.
greater than the maximum allowed shift amount, a
trap will occur.
ory location is attempted.
memory location is attempted.
attempted.
Note:
“GOTO #literal” instruction, where literal is
an unimplemented program memory address.
when
TRAP SOURCES
In the MAC class of instructions, wherein
the data space is split into X and Y data
space, unimplemented X space includes
all of Y space, and unimplemented Y
space includes all of X space.
they
occur.
Consequently,
DS70143D-page 49
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