PIC18F8621-I/PT Microchip Technology, PIC18F8621-I/PT Datasheet - Page 357

• Manufacturer Part Number: PIC18F8621-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8621-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.75KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F8621-I/PTR; PIC18F8621-I/PTR

FIGURE 27-24:
TABLE 27-26: A/D CONVERSION REQUIREMENTS
 2005 Microchip Technology Inc.
130
131
132
135
136
Note 1:
Param.
No.
Note 1: If the A/D clock source is selected as RC, a time of T
A/D DATA
SAMPLE
2:
3:
4:
5:
A/D CLK
ADRES
BSF ADCON0, GO
2: This is a minimal RC delay (typically 100 ns) which also disconnects the holding capacitor from the analog input.
T
T
T
T
T
Symbol
ADIF
AD
CNV
ACQ
SWC
AMP
GO
ADRES register may be read on the following T
See Section 20.0 “10-Bit Analog-to-Digital Converter (A/D) Module” for minimum conditions when input
voltage has changed more than 1 LSb.
The time for the holding capacitor to acquire the “New” input voltage when the voltage changes full scale
after the conversion (AV
50Ω.
On the next Q4 cycle of the device clock.
The time of the A/D clock period is dependent on the device frequency and the T
Q4
This allows the SLEEP instruction to be executed.
132
A/D Clock Period
Conversion Time (not including acquisition
time) (Note 1)
Acquisition Time (Note 3)
Switching Time from Convert → Sample
Amplifier Settling Time (Note 2)
A/D CONVERSION TIMING
(Note 2)
Characteristic
9
DD
to AV
8
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
PIC18F6X2X/8X2X
PIC18LF6X2X/8X2X
SS
PIC18F6525/6621/8525/8621
OLD_DATA
, or AV
7
CY
SS
. . .
SAMPLING STOPPED
is added before the A/D clock starts.
to AV
CY
. . .
DD
131
130
cycle.
). The source impedance (R
Min
1.6
3.0
2.0
3.0
11
15
10
—
1
2
(Note 4)
20
20
Max
6.0
9.0
12
—
—
—
1
(5)
(5)
Units
T
µs
µs
µs
µs
µs
µs
µs
AD
0
T
T
A/D RC mode
A/D RC mode
-40°C ≤ Temp ≤ +125°C
0°C ≤ Temp ≤ +125°C
This may be used if the
“new” input voltage has not
changed by more than 1 LSb
(i.e., 5 mV @ 5.12V) from the
last sampled voltage (as
stated on C
OSC
OSC
AD
S
) on the input channels is
clock divider.
NEW_DATA
DONE
based, V
based, V
Conditions
DS39612B-page 355
T
HOLD
CY
REF
REF
).
≥ 3.0V
full range