PIC18F8621-I/PT Microchip Technology, PIC18F8621-I/PT Datasheet - Page 272

• Manufacturer Part Number: PIC18F8621-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8621-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.75KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F8621-I/PTR; PIC18F8621-I/PTR

second block (Block 0) of 14 Kbytes.
PIC18F6525/6621/8525/8621
FIGURE 24-2:
24.4
The overall structure of the code protection on the
PIC18 Flash devices differs significantly from other
PICmicro devices.
The user program memory is divided on binary bound-
aries into four blocks of 16 Kbytes each. The first block is
further divided into a boot block of 2048 bytes and a
FIGURE 24-3:
DS39612B-page 270
Note
(INTCON<1>)
(INTCON<7>)
INSTRUCTION FLOW
Instruction
Fetched
Instruction
Executed
INTF Flag
GIEH bit
CLKO
INT pin
1:
2:
3:
4:
OSC1
Program Verification and
Code Protection
PC
Unimplemented, read ‘0’
(4)
XT, HS or LP Oscillator mode assumed.
GIE = 1 assumed. In this case, after wake-up, the processor jumps to the interrupt routine. If GIE = 0, execution will continue in-line.
T
CLKO is not available in these oscillator modes but shown here for timing reference.
OST
Inst(PC) = Sleep
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1
(PIC18FX525)
Inst(PC – 1)
= 1024 T
48 Kbytes
Boot Block
Block 0
Block 1
Block 2
PC
WAKE-UP FROM SLEEP THROUGH INTERRUPT
CODE-PROTECTED PROGRAM MEMORY FOR PIC18F6525/6621/8525/8621
DEVICES
MEMORY SIZE/DEVICE
OSC
(drawing not to scale). This delay will not occur for RC and EC Oscillator modes.
Inst(PC + 2)
Sleep
PC + 2
(PIC18FX621)
Boot Block
64 Kbytes
Processor in
Block 0
Block 1
Block 2
Block 3
Sleep
PC + 4
T
OST
(2)
000000h
0007FFh
000800h
003FFFh
004000h
007FFFh
008000h
00BFFFh
00C000h
00FFFFh
Address
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
Range
Inst(PC + 4)
Inst(PC + 2)
Each of the blocks has three code protection bits
associated with them. They are:
• Code-Protect bit (CPn)
• Write-Protect bit (WRTn)
• External Block Table Read bit (EBTRn)
Figure 24-3 shows the program memory organization
for 48 and 64-Kbyte devices and the specific code
protection bit associated with each block. The actual
locations of the bits are summarized in Table 24-3.
PC + 4
Interrupt Latency
Dummy Cycle
PC + 4
(1,2)
Block Code Protection
CPB, WRTB, EBTRB
CP0, WRT0, EBTR0
CP1, WRT1, EBTR1
CP2, WRT2, EBTR2
CP3, WRT3, EBTR3
Controlled By:
(3)
 2005 Microchip Technology Inc.
Dummy Cycle
Inst(0008h)
0008h
Inst(000Ah)
Inst(0008h)
000Ah