PIC18F8621-I/PT Microchip Technology, PIC18F8621-I/PT Datasheet - Page 233

• Manufacturer Part Number: PIC18F8621-I/PT
• Description: IC PIC MCU FLASH 32KX16 80TQFP
• Manufacturer: Microchip Technology
• Series: PIC® 18Fr

Specifications of PIC18F8621-I/PT

• Core Size: 8-Bit
• Program Memory Size: 64KB (32K x 16)
• Core Processor: PIC
• Speed: 40MHz
• Connectivity: EBI/EMI, I²C, SPI, UART/USART
• Peripherals: Brown-out Detect/Reset, LVD, POR, PWM, WDT
• Number Of I /o: 69
• Program Memory Type: FLASH
• Eeprom Size: 1K x 8
• Ram Size: 3.75K x 8
• Voltage - Supply (vcc/vdd): 4.2 V ~ 5.5 V
• Data Converters: A/D 16x10b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 80-TFQFP
• Controller Family/series: PIC18
• No. Of I/o's: 70
• Eeprom Memory Size: 1024Byte
• Ram Memory Size: 3.75KB
• Cpu Speed: 40MHz
• No. Of Timers: 5
• Processor Series: PIC18F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 3840 B
• Interface Type: MSSP, SPI, I2C, EUSART
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 69
• Number Of Timers: 5
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, ICE2000, ICE4000, DV164136, DM183032
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 16 Channel
• Package: 80TQFP
• Device Core: PIC
• Family Name: PIC18
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 5 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: XLT80PT3 - SOCKET TRAN ICE 80MQFP/TQFPAC164320 - MODULE SKT MPLAB PM3 80TQFPAC174011 - MODULE SKT PROMATEII 80TQFP
• Lead Free Status / Rohs Status: Details
• Other names: PIC18F8621-I/PTR; PIC18F8621-I/PTR

19.4
Synchronous Slave mode is entered by clearing bit
CSRC (TXSTAx<7>). This mode differs from the Syn-
chronous Master mode in that the shift clock is supplied
externally at the CKx pin (instead of being supplied
internally in Master mode). This allows the device to
transfer or receive data while in any low-power mode.
19.4.1
The operation of the Synchronous Master and Slave
modes are identical except in the case of the Sleep
mode.
If two words are written to the TXREGx and then the
SLEEP instruction is executed, the following will occur:
a)
b)
c)
d)
e)
TABLE 19-9:
 2005 Microchip Technology Inc.
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
TXREGx
TXSTAx
BAUDCONx
SPBRGHx
SPBRGx
Legend:
Note 1:
Name
The first word will immediately transfer to the
TSR register and transmit.
The second word will remain in the TXREGx
register.
Flag bit TXxIF will not be set.
When the first word has been shifted out of TSR,
the TXREGx register will transfer the second
word to the TSR and flag bit TXxIF will now be
set.
If enable bit TXxIE is set, the interrupt will wake
the chip from Sleep. If the global interrupt is
enabled, the program will branch to the interrupt
vector.
EUSART Synchronous Slave
Mode
x = unknown, – = unimplemented, read as ‘0’. Shaded cells are not used for synchronous slave transmission.
Enabled only in Microcontroller mode for PIC18F8525/8621 devices.
EUSART SYNCHRONOUS SLAVE
TRANSMIT
Enhanced USARTx Transmit Register
Enhanced USARTx Baud Rate Generator Register High Byte
Enhanced USARTx Baud Rate Generator Register Low Byte
GIE/GIEH
PSPIF
PSPIE
PSPIP
CSRC
SPEN
Bit 7
—
—
—
—
REGISTERS ASSOCIATED WITH SYNCHRONOUS SLAVE TRANSMISSION
(1)
(1)
(1)
PEIE/GIEL
RCIDL
ADIF
ADIE
ADIP
Bit 6
RX9
TX9
—
—
—
TMR0IE
RC1IE
RC1IP
RC2IE
RC2IP
RC1IF
RC2IF
SREN
TXEN
Bit 5
—
PIC18F6525/6621/8525/8621
INT0IE
CREN
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
SYNC
SCKP
Bit 4
TMR4IF
TMR4IE CCP5IE CCP4IE CCP3IE --00 0000
TMR4IP CCP5IP CCP4IP CCP3IP --11 1111
ADDEN
SENDB
BRG16
SSPIF
SSPIE
SSPIP
RBIE
Bit 3
To set up a Synchronous Slave Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
TMR0IF
CCP1IF
CCP1IE TMR2IE TMR1IE 0000 0000
CCP1IP TMR2IP TMR1IP 1111 1111
CCP5IF
BRGH
FERR
Bit 2
—
Enable the synchronous slave serial port by
setting bits SYNC and SPEN and clearing bit
CSRC.
Clear bits CREN and SREN.
If interrupts are desired, set enable bit TXxIE.
If 9-bit transmission is desired, set bit TX9.
Enable the transmission by setting enable bit
TXEN.
If 9-bit transmission is selected, the ninth bit
should be loaded in bit TX9D.
Start transmission by loading data to the
TXREGx register.
If using interrupts, ensure that the GIE and PEIE
bits in the INTCON register (INTCON<7:6>) are
set.
TMR2IF TMR1IF 0000 0000
CCP4IF
INT0IF
OERR
TRMT
WUE
Bit 1
CCP3IF
ABDEN
RX9D
TX9D
RBIF
Bit 0
0000 000x
--00 0000
0000 000x
0000 0000
0000 0010
-1-0 0-00
0000 0000
0000 0000
POR, BOR
Value on
DS39612B-page 231
0000 000u
0000 0000
0000 0000
1111 1111
--00 0000
--00 0000
--11 1111
0000 000x
0000 0000
0000 0010
-1-0 0-00
0000 0000
0000 0000
Value on
all other
Resets