PIC17C43-16/P Microchip Technology, PIC17C43-16/P Datasheet - Page 93

• Manufacturer Part Number: PIC17C43-16/P
• Description: IC MCU OTP 4KX16 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C43-16/P

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 454 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

13.3
In Master Synchronous mode, the data is transmitted in
a half-duplex manner; i.e. transmission and reception
do not occur at the same time: when transmitting data,
the reception is inhibited and vice versa. The synchro-
nous mode is entered by setting the SYNC
(TXSTA<4>) bit. In addition, the SPEN (RCSTA<7>) bit
is set in order to configure the RA5 and RA4 I/O ports
to CK (clock) and DT (data) lines respectively. The
Master mode indicates that the processor transmits the
master clock on the CK line. The Master mode is
entered by setting the CSRC (TXSTA<7>) bit.
13.3.1
The USART transmitter block diagram is shown in
Figure 13-3. The heart of the transmitter is the transmit
(serial) shift register (TSR). The shift register obtains its
data from the read/write transmit buffer TXREG.
TXREG is loaded with data in software. The TSR is not
loaded until the last bit has been transmitted from the
previous load. As soon as the last bit is transmitted, the
TSR is loaded with new data from TXREG (if available).
Once TXREG transfers the data to the TSR (occurs in
one T
is empty and the TXIF (PIR<1>) bit is set. This interrupt
can be enabled/disabled by setting/clearing the TXIE
bit (PIE<1>). TXIF will be set regardless of the state of
bit TXIE and cannot be cleared in software. It will reset
only when new data is loaded into TXREG. While TXIF
indicates the status of TXREG, TRMT (TXSTA<1>)
shows the status of the TSR. TRMT is a read only bit
which is set when the TSR is empty. No interrupt logic
is tied to this bit, so the user has to poll this bit in order
to determine if the TSR is empty. The TSR is not
mapped in data memory, so it is not available to the
user.
Transmission is enabled by setting the TXEN
(TXSTA<5>) bit. The actual transmission will not occur
until TXREG has been loaded with data. The first data
bit will be shifted out on the next available rising edge
of the clock on the RA5/TX/CK pin. Data out is stable
around the falling edge of the synchronous clock
(Figure 13-10). The transmission can also be started
by first loading TXREG and then setting TXEN. This is
advantageous when slow baud rates are selected,
since BRG is kept in RESET when the TXEN, CREN,
and SREN bits are clear. Setting the TXEN bit will start
the BRG, creating a shift clock immediately. Normally
when transmission is first started, the TSR is empty, so
a transfer to TXREG will result in an immediate transfer
to
Back-to-back transfers are possible.
Clearing TXEN during a transmission will cause the
transmission to be aborted and will reset the transmit-
ter. The RA4/RX/DT and RA5/TX/CK pins will revert to
hi-impedance. If either CREN or SREN are set during
a transmission, the transmission is aborted and the
1996 Microchip Technology Inc.
the TSR,
CY
at the end of the current BRG cycle), TXREG
USART Synchronous Master Mode
USART SYNCHRONOUS MASTER
TRANSMISSION
resulting
in
an
empty TXREG.
RA4/RX/DT pin reverts to a hi-impedance state (for a
reception). The RA5/TX/CK pin will remain an output if
the CSRC bit is set (internal clock). The transmitter
logic is not reset, although it is disconnected from the
pins. In order to reset the transmitter, the user has to
clear the TXEN bit. If the SREN bit is set (to interrupt an
ongoing transmission and receive a single word), then
after the single word is received, SREN will be cleared
and the serial port will revert back to transmitting, since
the TXEN bit is still set. The DT line will immediately
switch from hi-impedance receive mode to transmit
and start driving. To avoid this, TXEN should be
cleared.
In
TX9 (TXSTA<6>) bit should be set and the ninth bit
should be written to TX9D (TXSTA<0>). The ninth bit
must be written before writing the 8-bit data to TXREG.
This is because a data write to TXREG can result in an
immediate transfer of the data to the TSR (if the TSR is
empty). If the TSR was empty and TXREG was written
before writing the “new” TX9D, the “present” value of
TX9D is loaded.
Steps to follow when setting up a Synchronous Master
Transmission:
1.
2.
3.
4.
5.
6.
7.
8.
Writing the transmit data to the TXREG, then enabling
the transmit (setting TXEN) allows transmission to start
sooner then doing these two events in the reverse
order.
Note:
Initialize the SPBRG register for the appropriate
baud rate (see Baud Rate Generator Section for
details).
Enable the synchronous master serial port by
setting the SYNC, SPEN, and CSRC bits.
Ensure that the CREN and SREN bits are clear
(these bits override transmission when set).
If interrupts are desired, then set the TXIE bit
(the GLINTD bit must be clear and the PEIE bit
must be set).
If 9-bit transmission is desired, then set the TX9
bit.
Start transmission by loading data to the
TXREG register.
If 9-bit transmission is selected, the ninth bit
should be loaded in TX9D.
Enable the transmission by setting TXEN.
order
To terminate a transmission, either clear
the SPEN bit, or the TXEN bit. This will
reset the transmit logic, so that it will be in
the
re-enabled.
to
proper
select
state
9-bit
PIC17C4X
when
transmission,
DS30412C-page 93
transmit
the
is