PIC17C43-16/P Microchip Technology, PIC17C43-16/P Datasheet - Page 134

• Manufacturer Part Number: PIC17C43-16/P
• Description: IC MCU OTP 4KX16 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C43-16/P

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 454 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC17C4X
RRNCF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example 1:
Example 2:
DS30412C-page 134
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
WREG
REG
WREG
REG
WREG
REG
WREG
REG
Q1
=
=
=
=
=
=
=
=
register 'f'
Rotate Right f (no carry)
[ label ]
0
d
f<n>
f<0>
The contents of register 'f' are rotated
one bit to the right. If 'd' is 0 the result is
placed in WREG. If 'd' is 1 the result is
placed back in register 'f'.
1
1
RRNCF
RRNCF
None
Read
0010
Q2
?
1101 0111
0
1110 1011
?
1101 0111
1110 1011
1101 0111
f
[0,1]
255
d<n-1>;
d<7>
REG, 1
REG, 0
RRNCF f,d
000d
Execute
Q3
register f
ffff
destination
Write to
Q4
ffff
SETF
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example1:
Example2:
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
REG
WREG
REG
WREG
REG
WREG
REG
WREG
Q1
=
=
=
=
=
=
=
=
register 'f'
SETF
Set f
[ label ]
0
s
FFh
FFh
None
If 's' is 0, both the data memory location
'f' and WREG are set to FFh. If 's' is 1
only the data memory location 'f' is set
to FFh.
1
1
SETF
Read
0010
Q2
0xDA
0x05
0xFF
0xFF
0xDA
0x05
0xFF
0x05
f
[0,1]
1996 Microchip Technology Inc.
255
f;
d
REG, 1
SETF f,s
REG, 0
101s
Execute
Q3
ffff
register 'f'
and other
specified
register
Write
Q4
ffff