PIC17C43-16/P Microchip Technology, PIC17C43-16/P Datasheet - Page 105

• Manufacturer Part Number: PIC17C43-16/P
• Description: IC MCU OTP 4KX16 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C43-16/P

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 454 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

14.4
The Power-down mode is entered by executing a
SLEEP instruction. This clears the Watchdog Timer and
postscaler (if enabled). The PD bit is cleared and the
TO bit is set (in the CPUSTA register). In SLEEP mode,
the oscillator driver is turned off. The I/O ports maintain
their status (driving high, low, or hi-impedance).
The MCLR/V
(V
MCLR/V
14.4.1
The device can wake up from SLEEP through one of
the following events:
• A POR reset
• External reset input on MCLR/V
• WDT Reset (if WDT was enabled)
• Interrupt from RA0/INT pin, RB port change,
The following peripheral interrupts can wake-up from
SLEEP:
• Capture1 interrupt
• Capture2 interrupt
• USART synchronous slave transmit interrupt
• USART synchronous slave receive interrupt
Other peripherals can not generate interrupts since
during SLEEP, no on-chip Q clocks are present.
Any reset event will cause a device reset. Any interrupt
event is considered a continuation of program execu-
tion. The TO and PD bits in the CPUSTA register can
be used to determine the cause of device reset. The
FIGURE 14-9: WAKE-UP FROM SLEEP THROUGH INTERRUPT
Note 1: XT or LF oscillator mode assumed.
(RA0/INT pin)
1996 Microchip Technology Inc.
IHMC
T0CKI interrupt, or some Peripheral Interrupts
INSTRUCTION FLOW
CLKOUT(4)
GLINTD bit
Instruction
executed
Instruction
fetched
2: Tost = 1024Tosc (drawing not to scale). This delay will not be there for RC osc mode.
3: When GLINTD = 0 processor jumps to interrupt routine after wake-up. If GLINTD = 1, execution will continue in line.
4: CLKOUT is not available in these osc modes, but shown here for timing reference.
INTF flag
PC
). A WDT time-out RESET does not drive the
OSC1
PP
Power-down Mode (SLEEP)
WAKE-UP FROM SLEEP
INT
pin low.
PP
pin must be at a logic high level
Inst (PC) = SLEEP
Q1
Inst (PC-1)
Q2
PC
Q3
Q4
PP
pin
Q1
Inst (PC+1)
SLEEP
Q2
PC+1
Q3
Q4
Processor
in SLEEP
Q1
Q2
PD bit, which is set on power-up, is cleared when
SLEEP is invoked. The TO bit is cleared if WDT
time-out occurred (and caused wake-up).
When the SLEEP instruction is being executed, the next
instruction (PC + 1) is pre-fetched. For the device to
wake-up through an interrupt event, the corresponding
interrupt enable bit must be set (enabled). Wake-up is
regardless of the state of the GLINTD bit. If the GLINTD
bit is set (disabled), the device continues execution at
the instruction after the SLEEP instruction. If the
GLINTD bit is clear (enabled), the device executes the
instruction after the SLEEP instruction and then
branches to the interrupt vector address. In cases
where the execution of the instruction following SLEEP
is not desirable, the user should have a NOP after the
SLEEP instruction.
The WDT is cleared when the device wake from
SLEEP, regardless of the source of wake-up.
14.4.1.1
When the oscillator type is configured in XT or LF
mode, the Oscillator Start-up Timer (OST) is activated
on wake-up. The OST will keep the device in reset for
1024T
considering the interrupt response time when coming
out of SLEEP.
PC+2
Note:
Q3
Tost(2)
OSC
Q4
. This needs to be taken into account when
If the global interrupts are disabled
(GLINTD is set), but any interrupt source
has both its interrupt enable bit and the cor-
responding interrupt flag bits set, the
device will immediately wake-up from
sleep. The TO bit is set, and the PD bit is
cleared.
WAKE-UP DELAY
Q1
Inst (PC+2)
Inst (PC+1)
Q2
0004h
Q3
PIC17C4X
Q4
Interrupt Latency (2)
Q1
DS30412C-page 105
Dummy Cycle
Q2
0005h
Q3
Q4