PIC17C43-16/P Microchip Technology, PIC17C43-16/P Datasheet - Page 140

• Manufacturer Part Number: PIC17C43-16/P
• Description: IC MCU OTP 4KX16 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C43-16/P

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 454 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC17C4X
TLWT
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
Example:
DS30412C-page 140
Before Instruction
After Instruction
Before Instruction
After Instruction
Decode
t
RAM
TBLAT
RAM
TBLAT
t
RAM
TBLAT
RAM
TBLAT
Q1
=
=
=
=
=
=
=
=
=
=
register 'f'
Table Latch Write
[ label ] TLWT t,f
0
t
If t = 0,
If t = 1,
Data from file register 'f' is written into
the 16-bit table latch (TBLAT).
If t = 1; high byte is written
If t = 0; low byte is written
This instruction is used in conjunction
with TABLWT to transfer data from data
memory to program memory.
1
1
TLWT
None
Read
1010
Q2
f
f
0
0xB7
0x0000
0xB7
0x00B7
1
0xB7
0x0000
0xB7
0xB700
[0,1]
f
255
TBLATL;
TBLATH
t, RAM
01tx
(TBLATL = 0x00)
(TBLATL = 0xB7)
(TBLATL = 0x00)
(TBLATL = 0x00)
(TBLATH = 0x00)
(TBLATH = 0x00)
(TBLATH = 0x00)
(TBLATH = 0xB7)
Execute
Q3
ffff
TBLATH or
TBLATL
register
Write
Q4
ffff
TSTFSZ
Syntax:
Operands:
Operation:
Status Affected:
Encoding:
Description:
Words:
Cycles:
Q Cycle Activity:
If skip:
Example:
Before Instruction
After Instruction
Forced NOP
Decode
PC = Address(HERE)
If CNT
If CNT
Q1
Q1
PC
PC
register 'f'
Test f, skip if 0
[ label ] TSTFSZ f
0
skip if f = 0
None
If 'f' = 0, the next instruction, fetched
during the current instruction execution,
is discarded and an NOP is executed
making this a two-cycle instruction.
1
1 (2)
HERE
NZERO
ZERO
Read
NOP
0011
Q2
Q2
=
=
=
f
1996 Microchip Technology Inc.
255
0x00,
Address (ZERO)
0x00,
Address (NZERO)
:
TSTFSZ
:
0011
Execute
Execute
Q3
Q3
CNT
ffff
NOP
NOP
Q4
Q4
ffff