PIC17C43-16/P Microchip Technology, PIC17C43-16/P Datasheet - Page 48

• Manufacturer Part Number: PIC17C43-16/P
• Description: IC MCU OTP 4KX16 PWM 40DIP
• Manufacturer: Microchip Technology
• Series: PIC® 17Cr

Specifications of PIC17C43-16/P

• Core Size: 8-Bit
• Program Memory Size: 8KB (4K x 16)
• Core Processor: PIC
• Speed: 16MHz
• Connectivity: UART/USART
• Peripherals: POR, PWM, WDT
• Number Of I /o: 33
• Program Memory Type: OTP
• Ram Size: 454 x 8
• Voltage - Supply (vcc/vdd): 4.5 V ~ 6 V
• Oscillator Type: External
• Operating Temperature: 0°C ~ 70°C
• Package / Case: 40-DIP (0.600", 15.24mm)
• Controller Family/series: PIC17
• No. Of I/o's: 33
• Ram Memory Size: 454Byte
• Cpu Speed: 16MHz
• No. Of Timers: 4
• No. Of Pwm Channels: 2
• Embedded Interface Type: USART
• Rohs Compliant: Yes
• Processor Series: PIC17C
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 454 B
• Interface Type: SCI, USART
• Maximum Clock Frequency: 16 MHz
• Number Of Programmable I/os: 33
• Number Of Timers: 8
• Operating Supply Voltage: 2.5 V to 6 V
• Maximum Operating Temperature: + 70 C
• Mounting Style: Through Hole
• Development Tools By Supplier: ICE2000
• Minimum Operating Temperature: 0 C
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DVA17XP401 - DEVICE ADAPTER FOR PIC17C42AAC174001 - MODULE SKT PROMATEII 40DIP
• Eeprom Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Details

PIC17C4X
7.3
The table read allows the program memory to be read.
This allows constant data to be stored in the program
memory space, and retrieved into data memory when
needed. Example 7-2 reads the 16-bit value at pro-
gram memory address TBLPTR. After the dummy byte
has been read from the TABLATH, the TABLATH is
loaded with the 16-bit data from program memory
address TBLPTR + 1. The first read loads the data into
the latch, and can be considered a dummy read
(unknown data loaded into 'f'). INDF0 should be con-
figured for either auto-increment or auto-decrement.
FIGURE 7-7:
FIGURE 7-8:
DS30412C-page 48
Instruction
fetched
AD15:AD0
Instruction
executed
Table Reads
WR
ALE
OE
AD15:AD0
Instruction
fetched
Instruction
executed
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'1'
TABLRD TIMING
TABLRD TIMING (CONSECUTIVE TABLRD INSTRUCTIONS)
INST (PC-1)
TABLRD1
ALE
PC
WR
OE
Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4 Q1 Q2 Q3 Q4
'1'
TABLRD1 cycle1 TABLRD1 cycle2 TABLRD2 cycle1 TABLRD2 cycle2
INST (PC-1)
TABLRD
TABLRD2
PC
PC+1
TABLRD cycle1
Data read cycle
INST (PC+1)
PC+1
TBL1 Data in 1
EXAMPLE 7-2:
MOVLW
MOVWF
MOVLW
MOVWF
TABLRD
TLRD
TABLRD
INST (PC+2)
Data read cycle
TABLRD cycle2
PC+2
TBL
HIGH (TBL_ADDR) ; Load the Table
TBLPTRH
LOW (TBL_ADDR)
TBLPTRL
0,0,DUMMY
1, INDF0
0,1,INDF0
Data in
Data read cycle
TABLE READ
TBL2 Data in 2
INST (PC+2)
INST (PC+1)
1996 Microchip Technology Inc.
PC+2
;
;
;
; Dummy read,
;
; Read HI byte
;
; Read LO byte
;
;
Updates TABLATCH
address
of TABLATCH
of TABLATCH and
Update TABLATCH
INST (PC+3)
INST (PC+2)
PC+3