AT91M40800-33AU Atmel, AT91M40800-33AU Datasheet - Page 73

• Manufacturer Part Number: AT91M40800-33AU
• Description: IC ARM7 MCU 100 LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M40800-33AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100TQFP
• Device Core: ARM7TDMI
• Family Name: 91M
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: EBI/USART
• Number Of Timers: 3
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 33 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: EBI/EMI, UART/USART
• Ios: 32
• Memory Type: ROMless
• Number Of Bits: 32
• Package Type: 100-pin LQFP
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Cpu Family: 91M
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1354D–ATARM–08/02
Fast Interrupt Sequence
It is assumed that:
•
•
•
•
When NFIQ is asserted, if the bit F of CPSR is 0, the sequence is:
1. The CPSR is stored in SPSR_fiq, the current value of the Program Counter is
2. The ARM core enters FIQ Mode.
3. When the instruction loaded at address 0x1C is executed, the Program Counter
4. The previous step has effect to branch to the corresponding interrupt service
5. The Interrupt Handler can then proceed as required. It is not necessary to save
6. Finally, the Link Register (r14_fiq) is restored into the PC after decrementing it by
Note:
The Advanced Interrupt Controller has been programmed, AIC_SVR[0] is loaded
with fast interrupt service routine address and the fast interrupt is enabled.
The Instruction at address 0x1C(FIQ exception vector address) is:
ldr pc, [pc, # - &F20].
Nested Fast Interrupts are not needed by the user.
loaded in the FIQ link register (r14_fiq) and the Program Counter (r15) is loaded
with 0x1C. In the following cycle, during fetch at address 0x20, the ARM core
adjusts r14_fiq, decrementing it by 4.
is loaded with the value read in AIC_FVR. Reading the AIC_FVR has effect of
automatically clearing the fast interrupt (source 0 connected to the FIQ line), if it
has been programmed to be edge triggered. In this case only, it de-asserts the
NFIQ line on the processor.
routine. It is not necessary to save the Link Register(r14_fiq) and the
SPSR(SPSR_fiq) if nested fast interrupts are not needed.
registers r8 to r13 because FIQ Mode has its own dedicated registers and the
user r8 to r13 are banked. The other registers, r0 to r7, must be saved before
being used, and restored at the end (before the next step). Note that if the fast
interrupt is programmed to be level sensitive, the source of the interrupt must be
cleared during this phase in order to de-assert the NFIQ line.
4 (with instruction sub pc, lr, #4 for example). This has effect of returning from the
interrupt to whatever was being executed before, and of loading the CPSR with
the SPSR, masking or unmasking the fast interrupt depending on the state saved
in the SPSR.
The F bit in the SPSR is significant. If it is set, it indicates that the ARM core was just
about to mask FIQ interrupts when the mask instruction was interrupted. Hence when
the SPSR is restored, the interrupted instruction is completed (FIQ is masked).
AT91X40 Series
73