AT91M40800-33AU Atmel, AT91M40800-33AU Datasheet - Page 10

• Manufacturer Part Number: AT91M40800-33AU
• Description: IC ARM7 MCU 100 LQFP
• Manufacturer: Atmel
• Series: AT91SAMr

Specifications of AT91M40800-33AU

• Core Processor: ARM7
• Core Size: 16/32-Bit
• Speed: 33MHz
• Connectivity: EBI/EMI, UART/USART
• Peripherals: POR, WDT
• Number Of I /o: 32
• Program Memory Type: ROMless
• Ram Size: 8K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 3.6 V
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 100-LQFP
• Package: 100TQFP
• Device Core: ARM7TDMI
• Family Name: 91M
• Maximum Speed: 33 MHz
• Operating Supply Voltage: 2.5|3.3 V
• Data Bus Width: 32 Bit
• Number Of Programmable I/os: 32
• Interface Type: EBI/USART
• Number Of Timers: 3
• Processor Series: AT91Mx
• Core: ARM7TDMI
• Data Ram Size: 8 KB
• Maximum Clock Frequency: 33 MHz
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• 3rd Party Development Tools: JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
• Minimum Operating Temperature: - 40 C
• Eeprom Memory: 0 Bytes
• Input Output: 32
• Interface: EBI/EMI, UART/USART
• Ios: 32
• Memory Type: ROMless
• Number Of Bits: 32
• Package Type: 100-pin LQFP
• Programmable Memory: 0 Bytes
• Timers: 3-16-bit
• Voltage, Range: 1.8-3.6 V
• Cpu Family: 91M
• Device Core Size: 32b
• Frequency (max): 33MHz
• Program Memory Size: Not Required
• Total Internal Ram Size: 8KB
• # I/os (max): 32
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 100
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Program Memory Size: -
• Data Converters: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ROM Emulation
Boot Mode Select
Remap Command
Abort Control
10
AT91X40 Series
The AT91R40807 provides an ideal means of emulating the ROM version
AT91M40807. The secondary SRAM bank of the AT91R40807 is mapped to the same
address as the ROM of the AT91M40807. It is write-protected after a reset; writing 0x1
in the Memory Mode Register of the Special Function Module can disable this
protection.
At system power-up, the code is downloaded from an external non-volatile memory or
through a debugger to the on-chip secondary SRAM bank of the AT91R40807. After the
secondary SRAM bank write-protection is enabled, the application is in the same envi-
ronment as though it were running on an AT91M40807.
The ARM reset vector is at address 0x0. After the NRST line is released, the
ARM7TDMI executes the instruction stored at this address. This means that this
address must be mapped in non-volatile memory after the reset.
The input level on the BMS pin during the last 10 clock cycles before the rising edge of
the NRST selects the type of boot memory. The Boot Mode depends on BMS and
whether or not the AT91X40 Series Microcontroller has on-chip ROM or extended
SRAM (see Table 3).
The AT91R40807 supports boot in on-chip extended SRAM, for the purpose of emulat-
ing ROM versions. In this case, the microcontroller must first boot from external non-
volatile memory, and ensure that a valid program is downloaded in the on-chip extended
SRAM. Then, the NRST must be reasserted by external circuitry after the level on the
pin BMS is changed.
The pin BMS is multiplexed with the I/O line P24 that can be programmed after reset like
any standard PIO line.
Table 3. Boot Mode Select
The ARM vectors (Reset, Abort, Data Abort, Prefetch Abort, Undefined Instruction,
Interrupt, Fast Interrupt) are mapped from address 0x0 to address 0x20. In order to
allow these vectors to be redefined dynamically by the software, the AT91X40 Series
Microcontrollers use a remap command that enables switching between the boot mem-
ory and the internal primary SRAM bank addresses. The remap command is accessible
through the EBI User Interface, by writing one in RCB of EBI_RCR (Remap Control
Register). Performing a remap command is mandatory if access to the other external
devices (connected to chip selects 1 to 7) is required. The remap operation can only be
changed back by an internal reset or an NRST assertion.
The abort signal providing a Data Abort or a Prefetch Abort exception to the ARM7TDMI
is asserted in the following cases:
•
•
BMS
1
0
When accessing an undefined address in the EBI address space
When writing to a write-protected internal memory area on the AT91R40807
Product
AT91M40800
AT91R40807
AT91M40807
AT91R40008
All
Boot Memory
External 8-bit memory on NCS0
Internal 32-bit extended SRAM
Internal 32-bit ROM
External 8-bit memory on NCS0
External 16-bit memory on NCS0
1354D–ATARM–08/02