AT91M40800-33AU Atmel, AT91M40800-33AU Datasheet - Page 137

IC ARM7 MCU 100 LQFP

AT91M40800-33AU

Manufacturer Part Number
AT91M40800-33AU
Description
IC ARM7 MCU 100 LQFP
Manufacturer
Atmel
Series
AT91SAMr
Datasheets

Specifications of AT91M40800-33AU

Core Processor
ARM7
Core Size
16/32-Bit
Speed
33MHz
Connectivity
EBI/EMI, UART/USART
Peripherals
POR, WDT
Number Of I /o
32
Program Memory Type
ROMless
Ram Size
8K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 3.6 V
Oscillator Type
External
Operating Temperature
-40°C ~ 85°C
Package / Case
100-LQFP
Package
100TQFP
Device Core
ARM7TDMI
Family Name
91M
Maximum Speed
33 MHz
Operating Supply Voltage
2.5|3.3 V
Data Bus Width
32 Bit
Number Of Programmable I/os
32
Interface Type
EBI/USART
Number Of Timers
3
Processor Series
AT91Mx
Core
ARM7TDMI
Data Ram Size
8 KB
Maximum Clock Frequency
33 MHz
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
JTRACE-ARM-2M, MDK-ARM, RL-ARM, ULINK2
Minimum Operating Temperature
- 40 C
Eeprom Memory
0 Bytes
Input Output
32
Interface
EBI/EMI, UART/USART
Ios
32
Memory Type
ROMless
Number Of Bits
32
Package Type
100-pin LQFP
Programmable Memory
0 Bytes
Timers
3-16-bit
Voltage, Range
1.8-3.6 V
Cpu Family
91M
Device Core Size
32b
Frequency (max)
33MHz
Program Memory Size
Not Required
Total Internal Ram Size
8KB
# I/os (max)
32
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3V
Operating Supply Voltage (max)
3.6V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
100
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Eeprom Size
-
Program Memory Size
-
Data Converters
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant

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TC Channel Mode Register: Waveform Mode
Register Name: TC_CMR
Access Type:
Reset Value:
Offset:
• TCCLKS: Clock Selection
• CLKI: Clock Invert (Code Label TC_CLKI)
0 = Counter is incremented on rising edge of the clock.
1 = Counter is incremented on falling edge of the clock.
• BURST: Burst Signal Selection
• CPCSTOP: Counter Clock Stopped with RC Compare (Code Label TC_CPCSTOP)
0 = Counter clock is not stopped when counter reaches RC.
1 = Counter clock is stopped when counter reaches RC.
1354D–ATARM–08/02
WAVE = 1
CPCDIS
0
0
0
0
1
1
1
1
31
23
15
0
0
1
1
7
TCCLKS
BSWTRG
ASWTRG
BURST
0
0
1
1
0
0
1
1
Read/Write
0
0x04
CPCSTOP
CPCTRG
30
22
14
6
0
1
0
1
0
1
0
1
0
1
0
1
Clock Selected
MCK/2
MCK/8
MCK/32
MCK/128
MCK/1024
XC0
XC1
XC2
Selected BURST
The clock is not gated by an external signal.
XC0 is ANDed with the selected clock.
XC1 is ANDed with the selected clock.
XC2 is ANDed with the selected clock.
29
21
13
5
BEEVT
AEEVT
BURST
ENETRG
28
20
12
4
CLKI
27
19
11
3
BCPC
ACPC
EEVT
26
18
10
2
AT91X40 Series
TC_CLKS_MCK1024
TC_CLKS_MCK128
TC_CLKS_MCK32
TC_BURST_NONE
TC_CLKS_MCK2
TC_CLKS_MCK8
TC_BURST_XC0
TC_BURST_XC1
TC_BURST_XC2
TC_CLKS_XC0
TC_CLKS_XC1
TC_CLKS_XC2
TCCLKS
Code Label
Code Label
TC_BURST
TC_CLKS
25
17
9
1
EEVTEDG
BCPB
ACPA
24
16
8
0
137

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