ATMEGA169PV-8AU Atmel, ATMEGA169PV-8AU Datasheet - Page 37

• Manufacturer Part Number: ATMEGA169PV-8AU
• Description: IC AVR MCU 16K 8MHZ 1.8V 64-TQFP
• Manufacturer: Atmel
• Series: AVR® ATmegar

Specifications of ATMEGA169PV-8AU

• Core Processor: AVR
• Core Size: 8-Bit
• Speed: 8MHz
• Connectivity: SPI, UART/USART, USI
• Peripherals: Brown-out Detect/Reset, LCD, POR, PWM, WDT
• Number Of I /o: 54
• Program Memory Size: 16KB (8K x 16)
• Program Memory Type: FLASH
• Eeprom Size: 512 x 8
• Ram Size: 1K x 8
• Voltage - Supply (vcc/vdd): 1.8 V ~ 5.5 V
• Data Converters: A/D 8x10b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Package / Case: 64-TQFP, 64-VQFP
• Processor Series: ATMEGA16x
• Core: AVR8
• Data Bus Width: 8 bit
• Data Ram Size: 1 KB
• Interface Type: SPI, USART, USI
• Maximum Clock Frequency: 8 MHz
• Number Of Programmable I/os: 54
• Number Of Timers: 3
• Maximum Operating Temperature: + 85 C
• Mounting Style: SMD/SMT
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 10 bit, 8 Channel
• Cpu Family: ATmega
• Device Core: AVR
• Device Core Size: 8b
• Frequency (max): 8MHz
• Total Internal Ram Size: 1KB
• # I/os (max): 54
• Number Of Timers - General Purpose: 3
• Operating Supply Voltage (typ): 2.5/3.3/5V
• Operating Supply Voltage (max): 5.5V
• Operating Supply Voltage (min): 1.8V
• Instruction Set Architecture: RISC
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Mounting: Surface Mount
• Pin Count: 64
• Package Type: TQFP
• Package: 64TQFP
• Family Name: ATmega
• Maximum Speed: 8 MHz
• Operating Supply Voltage: 2.5|3.3|5 V
• Controller Family/series: AVR MEGA
• No. Of I/o's: 54
• Eeprom Memory Size: 512Byte
• Ram Memory Size: 1KB
• Cpu Speed: 8MHz
• Rohs Compliant: Yes
• For Use With: ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

8.8
8.9
8.10
8018P–AVR–08/10
Timer/Counter Oscillator
Clock Output Buffer
System Clock Prescaler
ATmega169P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter
Oscillator. See
crystal requirements.
ATmega169P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and
XTAL2. When using the Timer/Counter Oscillator, the system clock needs to be four times the
oscillator frequency. Due to this and the pin sharing, the Timer/Counter Oscillator can only be
used when the Calibrated Internal RC Oscillator is selected as system clock source.
Applying an external clock source to TOSC1 can be done if EXTCLK in the ASSR Register is
written to logic one. See
description on selecting external clock as input instead of a 32.768 kHz watch crystal.
When the CKOUT Fuse is programmed, the system Clock will be output on CLKO. This mode is
suitable when chip clock is used to drive other circuits on the system. The clock will be output
also during reset and the normal operation of I/O pin will be overridden when the fuse is pro-
grammed. Any clock source, including internal RC Oscillator, can be selected when CLKO
serves as clock output. If the System Clock Prescaler is used, it is the divided system clock that
is output when the CKOUT Fuse is programmed.
The ATmega169P system clock can be divided by setting the
ter” on page
consumption when the requirement for processing power is low. This can be used with all clock
source options, and it will affect the clock frequency of the CPU and all synchronous peripherals.
clk
When switching between prescaler settings, the System Clock Prescaler ensures that no
glitches occur in the clock system and that no intermediate frequency is higher than neither the
clock frequency corresponding to the previous setting, nor the clock frequency corresponding to
the new setting.
The ripple counter that implements the prescaler runs at the frequency of the undivided clock,
which may be faster than the CPU’s clock frequency. Hence, it is not possible to determine the
state of the prescaler – even if it were readable, and the exact time it takes to switch from one
clock division to another cannot be exactly predicted. From the time the CLKPS values are writ-
ten, it takes between T1 + T2 and T1 + 2 × T2 before the new clock frequency is active. In this
interval, 2 active clock edges are produced. Here, T1 is the previous clock period, and T2 is the
period corresponding to the new prescaler setting.
To avoid unintentional changes of clock frequency, a special write procedure must be followed
to change the CLKPS bits:
1. Write the Clock Prescaler Change Enable (CLKPCE) bit to one and all other bits in
2. Within four cycles, write the desired value to CLKPS while writing a zero to CLKPCE.
Interrupts must be disabled when changing prescaler setting to make sure the write procedure is
not interrupted.
I/O
CLKPR to zero.
, clk
ADC
, clk
38. This feature can be used to decrease the system clock frequency and power
”Low-frequency Crystal Oscillator” on page 34
CPU
, and clk
”Asynchronous operation of the Timer/Counter” on page 150
FLASH
are divided by a factor as shown in
”CLKPR – Clock Prescale Regis-
for details on the oscillator and
Table
ATmega169P
8-13.
for further
37