ATMEGA169PV-8AU Atmel, ATMEGA169PV-8AU Datasheet

IC AVR MCU 16K 8MHZ 1.8V 64-TQFP

ATMEGA169PV-8AU

Manufacturer Part Number
ATMEGA169PV-8AU
Description
IC AVR MCU 16K 8MHZ 1.8V 64-TQFP
Manufacturer
Atmel
Series
AVR® ATmegar
Datasheets

Specifications of ATMEGA169PV-8AU

Core Processor
AVR
Core Size
8-Bit
Speed
8MHz
Connectivity
SPI, UART/USART, USI
Peripherals
Brown-out Detect/Reset, LCD, POR, PWM, WDT
Number Of I /o
54
Program Memory Size
16KB (8K x 16)
Program Memory Type
FLASH
Eeprom Size
512 x 8
Ram Size
1K x 8
Voltage - Supply (vcc/vdd)
1.8 V ~ 5.5 V
Data Converters
A/D 8x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Package / Case
64-TQFP, 64-VQFP
Processor Series
ATMEGA16x
Core
AVR8
Data Bus Width
8 bit
Data Ram Size
1 KB
Interface Type
SPI, USART, USI
Maximum Clock Frequency
8 MHz
Number Of Programmable I/os
54
Number Of Timers
3
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
Minimum Operating Temperature
- 40 C
On-chip Adc
10 bit, 8 Channel
Cpu Family
ATmega
Device Core
AVR
Device Core Size
8b
Frequency (max)
8MHz
Total Internal Ram Size
1KB
# I/os (max)
54
Number Of Timers - General Purpose
3
Operating Supply Voltage (typ)
2.5/3.3/5V
Operating Supply Voltage (max)
5.5V
Operating Supply Voltage (min)
1.8V
Instruction Set Architecture
RISC
Operating Temp Range
-40C to 85C
Operating Temperature Classification
Industrial
Mounting
Surface Mount
Pin Count
64
Package Type
TQFP
Package
64TQFP
Family Name
ATmega
Maximum Speed
8 MHz
Operating Supply Voltage
2.5|3.3|5 V
Controller Family/series
AVR MEGA
No. Of I/o's
54
Eeprom Memory Size
512Byte
Ram Memory Size
1KB
Cpu Speed
8MHz
Rohs Compliant
Yes
For Use With
ATSTK600-TQFP64 - STK600 SOCKET/ADAPTER 64-TQFP770-1007 - ISP 4PORT ATMEL AVR MCU SPI/JTAG770-1005 - ISP 4PORT FOR ATMEL AVR MCU JTAG770-1004 - ISP 4PORT FOR ATMEL AVR MCU SPIATAVRISP2 - PROGRAMMER AVR IN SYSTEMATJTAGICE2 - AVR ON-CHIP D-BUG SYSTEMATAVRBFLY - KIT EVALUATION AVR BUTTERFLYATSTK502 - MOD EXPANSION AVR STARTER 500ATSTK500 - PROGRAMMER AVR STARTER KIT
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
ATMEGA169PV-8AU
Manufacturer:
Atmel
Quantity:
10 000
Part Number:
ATMEGA169PV-8AU
Manufacturer:
ATMEL/爱特梅尔
Quantity:
20 000
Part Number:
ATMEGA169PV-8AUR
Manufacturer:
Atmel
Quantity:
10 000
Features
High Performance, Low Power Atmel
Advanced RISC Architecture
High Endurance Non-volatile Memory segments
JTAG (IEEE std. 1149.1 compliant) Interface
Peripheral Features
Special Microcontroller Features
I/O and Packages
Speed Grade:
Temperature range:
Ultra-Low Power Consumption
– 130 Powerful Instructions – Most Single Clock Cycle Execution
– 32 × 8 General Purpose Working Registers
– Fully Static Operation
– Up to 16 MIPS Throughput at 16 MHz
– On-Chip 2-cycle Multiplier
– 16 Kbytes of In-System Self-programmable Flash program memory
– 512 Bytes EEPROM
– 1 Kbytes Internal SRAM
– Write/Erase cycles: 10,000 Flash/100,000 EEPROM
– Data retention: 20 years at 85°C/100 years at 25°C
– Optional Boot Code Section with Independent Lock Bits
– Programming Lock for Software Security
– Boundary-scan Capabilities According to the JTAG Standard
– Extensive On-chip Debug Support
– Programming of Flash, EEPROM, Fuses, and Lock Bits through the JTAG Interface
– 4 × 25 Segment LCD Driver
– Two 8-bit Timer/Counters with Separate Prescaler and Compare Mode
– One 16-bit Timer/Counter with Separate Prescaler, Compare Mode, and Capture
– Real Time Counter with Separate Oscillator
– Four PWM Channels
– 8-channel, 10-bit ADC
– Programmable Serial USART
– Master/Slave SPI Serial Interface
– Universal Serial Interface with Start Condition Detector
– Programmable Watchdog Timer with Separate On-chip Oscillator
– On-chip Analog Comparator
– Interrupt and Wake-up on Pin Change
– Power-on Reset and Programmable Brown-out Detection
– Internal Calibrated Oscillator
– External and Internal Interrupt Sources
– Five Sleep Modes: Idle, ADC Noise Reduction, Power-save, Power-down, and
– 54 Programmable I/O Lines
– 64-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN
– ATmega169PV: 0 - 4 MHz @ 1.8V - 5.5V, 0 - 8 MHz @ 2.7V - 5.5V
– ATmega169P: 0 - 8 MHz @ 2.7V - 5.5V, 0 - 16 MHz @ 4.5V - 5.5V
– -40°C to 85°C Industrial
– Active Mode:
– Power-down Mode:
– Power-save Mode:
Mode
Standby
In-System Programming by On-chip Boot Program
True Read-While-Write Operation
1 MHz, 1.8V: 330 µA
32 kHz, 1.8V: 10 µA (including Oscillator)
32 kHz, 1.8V: 25 µA (including Oscillator and LCD)
0.1 µA at 1.8V
0.6 µA at 1.8V (Including 32 kHz RTC)
®
AVR
®
8-Bit Microcontroller
(1)
8-bit
Microcontroller
with 16K Bytes
In-System
Programmable
Flash
ATmega169P
ATmega169PV
Preliminary
Rev. 8018P–AVR–08/10

Related parts for ATMEGA169PV-8AU

ATMEGA169PV-8AU Summary of contents

Page 1

... I/O and Packages – 54 Programmable I/O Lines – 64-lead TQFP, 64-pad QFN/MLF and 64-pad DRQFN • Speed Grade: – ATmega169PV MHz @ 1.8V - 5.5V MHz @ 2.7V - 5.5V – ATmega169P MHz @ 2.7V - 5.5V MHz @ 4.5V - 5.5V • Temperature range: – -40°C to 85°C Industrial • ...

Page 2

Pin Configurations 1.1 Pinout - TQFP/QFN/MLF Figure 1-1. 64A (TQFP) and 64M1 (QFN/MLF) Pinout ATmega169P LCDCAP 1 (RXD/PCINT0) PE0 2 (TXD/PCINT1) PE1 3 (XCK/AIN0/PCINT2) PE2 4 (AIN1/PCINT3) PE3 5 (USCK/SCL/PCINT4) PE4 6 (DI/SDA/PCINT5) PE5 7 (DO/PCINT6) PE6 8 (CLKO/PCINT7) ...

Page 3

Pinout - DRQFN Figure 1-2. 64MC (DRQFN) Pinout ATmega169P Top view Table 1-1. DRQFN-64 Pinout ATmega169P. A1 PE0 A9 B1 VLCDCAP B8 A2 PE1 ...

Page 4

Overview The ATmega169P is a low-power CMOS 8-bit microcontroller based on the AVR enhanced RISC architecture. By execut- ing powerful instructions in a single clock cycle, the ATmega169P achieves throughputs approaching 1 MIPS per MHz allowing the system designer ...

Page 5

... Application Flash section is updated, providing true Read-While-Write operation. By combining an 8-bit RISC CPU with In-System Self-Programmable Flash on a monolithic chip, the Atmel ATmega169P is a powerful microcontroller that provides a highly flex- ible and cost effective solution to many embedded control applications. ...

Page 6

Pin Descriptions 2.2.1 VCC Digital supply voltage. 2.2.2 GND Ground. 2.2.3 Port A (PA7:PA0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port A output buffers have symmetrical drive characteristics ...

Page 7

Port E (PE7:PE0) Port 8-bit bi-directional I/O port with internal pull-up resistors (selected for each bit). The Port E output buffers have symmetrical drive characteristics with both high sink and source capability. As inputs, Port E ...

Page 8

AREF This is the analog reference pin for the A/D Converter. 2.2.15 LCDCAP An external capacitor (typical > 470 nF) must be connected to the LCDCAP pin as shown in ure 23-2 on page capacitance reduces ripple on V ...

Page 9

... Resources A comprehensive set of development tools, application notes and datasheets are available for download on http://www.atmel.com/avr. Note: 4. Data Retention Reliability Qualification results show that the projected data retention failure rate is much less than 1 PPM over 20 years at 85°C or 100 years at 25°C. ...

Page 10

About Code Examples This documentation contains simple code examples that briefly show how to use various parts of the device. Be aware that not all C compiler vendors include bit definitions in the header files and interrupt handling in ...

Page 11

AVR CPU Core 6.1 Introduction This section discusses the AVR core architecture in general. The main function of the CPU core is to ensure correct program execution. The CPU must therefore be able to access memories, perform calculations, control ...

Page 12

The fast-access Register File contains 32 × 8-bit general purpose working registers with a single clock cycle access time. This allows single-cycle Arithmetic Logic Unit (ALU) operation typ- ical ALU operation, two operands are output from the Register ...

Page 13

Stack Pointer The Stack is mainly used for storing temporary data, for storing local variables and for storing return addresses after interrupts and subroutine calls. Note that the Stack is implemented as growing from higher to lower memory locations. ...

Page 14

SPH and SPL – Stack Pointer Bit 0x3E (0x5E) 0x3D (0x5D) Read/Write Initial Value 6.5 Instruction Execution Timing This section describes the general access timing concepts for instruction execution. The AVR CPU is driven by the CPU clock clk ...

Page 15

Reset and Interrupt Handling The AVR provides several different interrupt sources. These interrupts and the separate Reset Vector each have a separate program vector in the program memory space. All interrupts are assigned individual enable bits which must be ...

Page 16

Assembly Code Example in r16, SREG cli sbi EECR, EEMWE sbi EECR, EEWE out SREG, r16 C Code Example char cSREG; cSREG = SREG; /* store SREG value */ /* disable interrupts during timed sequence */ __disable_interrupt(); EECR |= (1<<EEMWE); ...

Page 17

Status Register The Status Register contains information about the result of the most recently executed arithme- tic instruction. This information can be used for altering program flow in order to perform conditional operations. Note that the Status Register is ...

Page 18

Bit 1 – Z: Zero Flag The Zero Flag Z indicates a zero result in an arithmetic or logic operation. See the “Instruction Set Description” for detailed information. • Bit 0 – C: Carry Flag The Carry Flag C ...

Page 19

The X-register, Y-register, and Z-register The registers R26..R31 have some added functions to their general purpose usage. These reg- isters are 16-bit address pointers for indirect addressing of the data space. The three indirect address registers X, Y, and ...

Page 20

AVR Memories This section describes the different memories in the ATmega169P. The AVR architecture has two main memory spaces, the Data Memory and the Program Memory space. In addition, the ATmega169P features an EEPROM Memory for data storage. All ...

Page 21

SRAM Data Memory Figure 7-2 The ATmega169P is a complex microcontroller with more peripheral units than can be sup- ported within the 64 locations reserved in the Opcode for the IN and OUT instructions. For the Extended I/O space ...

Page 22

Data Memory Access Times This section describes the general access timing concepts for internal memory access. The internal data SRAM access is performed in two clk Figure 7-3. 8018P–AVR–08/10 On-chip Data SRAM Access Cycles T1 clk CPU Address Compute ...

Page 23

EEPROM Data Memory The ATmega169P contains 512 bytes of data EEPROM memory organized as a separate data space, in which single bytes can be read and written. The EEPROM has an endurance of at least 100,000 write/erase ...

Page 24

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft- ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set, the CPU is ...

Page 25

The following code examples show one assembly and one C function for writing to the EEPROM. To avoid that interrupts will occur during execution of these functions, the examples assume that interrupts are controlled (for example by disabling interrupts globally). ...

Page 26

The next code examples show assembly and C functions for reading the EEPROM. The exam- ples assume that interrupts are controlled so that no interrupts will occur during execution of these functions. Assembly Code Example EEPROM_read: C Code Example unsigned ...

Page 27

EEPROM Write During Power-down Sleep Mode When entering Power-down sleep mode while an EEPROM write operation is active, the EEPROM write operation will continue, and will complete before the Write Access time has passed. However, when the write operation ...

Page 28

General Purpose I/O Registers The ATmega169P contains three General Purpose I/O Registers. These registers can be used for storing any information, and they are particularly useful for storing global variables and Sta- tus Flags. General Purpose I/O Registers within ...

Page 29

EEDR – EEPROM Data Register Bit 0x20 (0x40) Read/Write Initial Value • Bits 7:0 – EEDR7:0: EEPROM Data For the EEPROM write operation, the EEDR Register contains the data to be written to the EEPROM in the address given ...

Page 30

System Clock and Clock Options 8.1 Clock Systems and their Distribution Figure 8-1 need not be active at a given time. In order to reduce power consumption, the clocks to modules not being used can be halted by using ...

Page 31

Asynchronous Timer Clock – clk The Asynchronous Timer clock allows the Asynchronous Timer/Counter and the LCD controller to be clocked directly from an external clock or an external 32 kHz clock crystal. The dedicated clock domain allows using this ...

Page 32

Default Clock Source The device is shipped with CKSEL = “0010”, SUT = “10”, and CKDIV8 programmed. The default clock source setting is the Internal RC Oscillator with longest start-up time and an initial system clock prescaling of 8. ...

Page 33

Crystal Oscillator XTAL1 and XTAL2 are input and output, respectively inverting amplifier which can be con- figured for use as an On-chip Oscillator, as shown in ceramic resonator may be used. C1 and C2 should always be ...

Page 34

The CKSEL0 Fuse together with the SUT1..0 Fuses select the start-up times as shown in 8-6. Table 8-6. CKSEL0 Notes: 8.6 Low-frequency Crystal Oscillator The Low-frequency Crystal Oscillator is optimized for use ...

Page 35

Table 8-8. ATmega169P The capacitance (Ce + Ci) needed at each TOSC pin can be calculated by using: where optional external capacitors as described the pin capacitance the ...

Page 36

External Clock To drive the device from an external clock source, XTAL1 should be driven as shown in 8-3. To run the device on an external clock, the CKSEL Fuses must be programmed to “0000”. Figure 8-3. When this ...

Page 37

Timer/Counter Oscillator ATmega169P uses the same crystal oscillator for Low-frequency Oscillator and Timer/Counter Oscillator. See crystal requirements. ATmega169P share the Timer/Counter Oscillator Pins (TOSC1 and TOSC2) with XTAL1 and XTAL2. When using the Timer/Counter Oscillator, the system clock needs ...

Page 38

Register Description 8.11.1 OSCCAL – Oscillator Calibration Register Bit (0x66) Read/Write Initial Value • Bits 7:0 – CAL7:0: Oscillator Calibration Value The Oscillator Calibration Register is used to trim the Calibrated Internal RC Oscillator to remove process variations from ...

Page 39

This feature should be used if the selected clock source has a higher frequency than the maximum frequency of the device at the present operat- ing conditions. Note that any ...

Page 40

Power Management and Sleep Modes Sleep modes enable the application to shut down unused modules in the MCU, thereby saving- power. The AVR provides various sleep modes allowing the user to tailor the power consumption to the application’s requirements. ...

Page 41

Idle Mode When the SM2..0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode, stopping the CPU but allowing LCD controller, the SPI, USART, Analog Comparator, ADC, USI, Timer/Counters, Watchdog, and the interrupt system ...

Page 42

Power-save Mode When the SM2..0 bits are written to 011, the SLEEP instruction makes the MCU enter Power- save mode. This mode is identical to Power-down, with one exception: If Timer/Counter2 and/or the LCD controller are enabled, they will ...

Page 43

Minimizing Power Consumption There are several issues to consider when trying to minimize the power consumption in an AVR controlled system. In general, sleep modes should be used as much as possible, and the sleep mode should be selected ...

Page 44

Port Pins When entering a sleep mode, all port pins should be configured to use minimum power. The most important is then to ensure that no pins drive resistive loads. In sleep modes where both the I/O clock (clk ...

Page 45

Register Description 9.9.1 SMCR – Sleep Mode Control Register The Sleep Mode Control Register contains control bits for power management. Bit 0x33 (0x53) Read/Write Initial Value • Bits – SM2:0: Sleep Mode Select Bits 2, 1, ...

Page 46

Bit 3 - PRTIM1: Power Reduction Timer/Counter1 Writing a logic one to this bit shuts down the Timer/Counter1 module. When the Timer/Counter1 is enabled, operation will continue like before the shutdown. • Bit 2 - PRSPI: Power Reduction Serial ...

Page 47

System Control and Reset 10.1 Resetting the AVR During reset, all I/O Registers are set to their initial values, and the program starts execution from the Reset Vector. The instruction placed at the Reset Vector must be a JMP ...

Page 48

Figure 10-1. Reset Logic BODLEVEL [2..0] 10.2.1 Power-on Reset A Power-on Reset (POR) pulse is generated by an On-chip detection circuit. The detection level is defined below the detection level. The POR circuit can be used to ...

Page 49

Figure 10-3. MCU Start-up, RESET Extended Externally TIME-OUT INTERNAL 10.2.2 External Reset An External Reset is generated by a low level on the RESET pin. Reset pulses longer than the minimum pulse width (see reset, even if the clock is ...

Page 50

Brown-out Detection ATmega169P has an On-chip Brown-out Detection (BOD) circuit for monitoring the V during operation by comparing fixed trigger level. The trigger level for the BOD can be selected by the BODLEVEL Fuses. The trigger ...

Page 51

Internal Voltage Reference ATmega169P features an internal bandgap reference. This reference is used for Brown-out Detection, and it can be used as an input to the Analog Comparator or the ADC. 10.3.1 Voltage Reference Enable Signals and Start-up Time ...

Page 52

Figure 10-7. Watchdog Timer 10.4.1 Timed Sequences for Changing the Configuration of the Watchdog Timer The sequence for changing configuration differs slightly between the two safety levels. Separate procedures are described for each level. 10.4.1.1 Safety Level 1 In this ...

Page 53

Assembly Code Example WDT_off: C Code Example void WDT_off(void Note: 8018P–AVR–08/10 (1) ; Reset WDT wdr ; Write logical one to WDCE and WDE in r16, WDTCR ori r16, (1<<WDCE)|(1<<WDE) out WDTCR, r16 ; Turn off WDT ldi ...

Page 54

Register Description 10.5.1 MCUSR – MCU Status Register The MCU Status Register provides information on which reset source caused an MCU reset. Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – JTRF: JTAG Reset Flag This bit is ...

Page 55

Bit 3 – WDE: Watchdog Enable When the WDE is written to logic one, the Watchdog Timer is enabled, and if the WDE is written to logic zero, the Watchdog Timer function is disabled. WDE can only be cleared ...

Page 56

Interrupts This section describes the specifics of the interrupt handling as performed in ATmega169P. For a general explanation of the AVR interrupt handling, refer to page 15. 11.1 Interrupt Vectors in ATmega169P Table 11-1. Vector No ...

Page 57

Table 11-2 on page 57 tions of BOOTRST and IVSEL settings. If the program never enables an interrupt source, the Interrupt Vectors are not used, and regular program code can be placed at these locations. This is also the case ...

Page 58

When the BOOTRST Fuse is unprogrammed, the Boot section size set to 2 Kbytes and the IVSEL bit in the MCUCR Register is set before any interrupts are enabled, the most typical and general program setup ...

Page 59

Moving Interrupts Between Application and Boot Space The General Interrupt Control Register controls the placement of the Interrupt Vector table, see ”MCUCR – MCU Control Register” on page To avoid unintentional changes ...

Page 60

Assembly Code Example Move_interrupts: ; Get MCUCR in r16, MCUCR mov r17, r16 ; Enable change of Interrupt Vectors ori r16, (1<<IVCE) out MCUCR, r16 ; Move interrupts to Boot Flash section ori r17, (1<<IVSEL) out MCUCR, r17 ret C ...

Page 61

External Interrupts The External Interrupts are triggered by the INT0 pin or any of the PCINT15..0 pins. Observe that, if enabled, the interrupts will trigger even if the INT0 or PCINT15..0 pins are configured as outputs. This feature provides ...

Page 62

Register Description 12.2.1 EICRA – External Interrupt Control Register A The External Interrupt Control Register A contains control bits for interrupt sense control. Bit (0x69) Read/Write Initial Value • Bit 1, 0 – ISC01, ISC00: Interrupt Sense Control 0 ...

Page 63

INT0 is configured as an output. The corresponding interrupt of External Interrupt Request 0 is executed from the INT0 Interrupt Vector. 12.2.3 EIFR – External Interrupt Flag Register Bit 0x1C (0x3C) Read/Write Initial Value • Bit ...

Page 64

PCMSK0 – Pin Change Mask Register 0 Bit (0x6B) Read/Write Initial Value • Bit 7:0 – PCINT7:0: Pin Change Enable Mask 7:0 Each PCINT7:0 bit selects whether pin change interrupt is enabled on the corresponding I/O pin. If PCINT7:0 ...

Page 65

I/O-Ports 13.1 Overview All AVR ports have true Read-Modify-Write functionality when used as general digital I/O ports. This means that the direction of one port pin can be changed without unintentionally changing the direction of any other pin with ...

Page 66

Ports as General Digital I/O The ports are bi-directional I/O ports with optional internal pull-ups. tional description of one I/O-port pin, here generically called Pxn. Figure 13-2. General Digital I/O Note: 13.2.1 Configuring the Pin Each port pin consists ...

Page 67

Toggling the Pin Writing a logic one to PINxn toggles the value of PORTxn, independent on the value of DDRxn. Note that the SBI instruction can be used to toggle one single bit in a port. 13.2.3 Switching Between ...

Page 68

Figure 13-3. Synchronization when Reading an Externally Applied Pin value INSTRUCTIONS Consider the clock period starting shortly after the first falling edge of the system clock. The latch is closed when the clock is low, and goes transparent when the ...

Page 69

Assembly Code Example C Code Example unsigned char i; Note: 13.2.5 ...

Page 70

Unconnected Pins If some pins are unused recommended to ensure that these pins have a defined level. Even though most of the digital inputs are disabled in the deep sleep modes as described above, float- ing inputs ...

Page 71

Alternate Port Functions Most port pins have alternate functions in addition to being general digital I/Os. shows how the port pin control signals from the simplified ridden by alternate functions. The overriding signals may not be present in all ...

Page 72

Table 13-2. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO The following subsections shortly describe the alternate functions for each port, and relate the overriding signals to the alternate function. Refer to the alternate function ...

Page 73

Alternate Functions of Port A The Port A has an alternate function as COM0:3 and SEG0:3 for the LCD Controller. Table 13-3. Table 13-4 signals shown in Table 13-4. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE ...

Page 74

Table 13-5. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.2 Alternate Functions of Port B The Port B pins with alternate functions are shown in Table 13-6. Port Pin PB7 PB6 PB5 PB4 PB3 ...

Page 75

OC1B/PCINT14, Bit 6 OC1B, Output Compare Match B output: The PB6 pin can serve as an external output for the Timer/Counter1 Output Compare B. The pin has to be configured as an output (DDB6 set (one)) to serve this ...

Page 76

When the SPI is enabled as a Master, the data direction of this pin is controlled by DDB0. When the pin is forced input, the pull-up can still be controlled by the PORTB0 bit. PCINT8, Pin ...

Page 77

Table 13-8. Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.3 Alternate Functions of Port C The Port C has an alternate function as the SEG5:12 for the LCD Controller. Table 13-9. 8018P–AVR–08/10 Overriding Signals ...

Page 78

Table 13-10 shown in Table 13-10. Overriding Signals for Alternate Functions in PC7..PC4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-11. Overriding Signals for Alternate Functions in PC3..PC0 Signal Name PUOE PUOV DDOE ...

Page 79

Alternate Functions of Port D The Port D pins with alternate functions are shown in Table 13-12. Port D Pins Alternate Functions Port Pin PD7 PD6 PD5 PD4 PD3 PD2 PD1 PD0 The alternate pin configuration is as follows: ...

Page 80

Table 13-13 shown in Table 13-13. Overriding Signals for Alternate Functions PD7..PD4 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Table 13-14. Overriding Signals for Alternate Functions in PD3..PD0 Signal Name PUOE PUOV DDOE DDOV ...

Page 81

Alternate Functions of Port E The Port E pins with alternate functions are shown in Table 13-15. Port E Pins Alternate Functions Port Pin PE7 PE6 PE5 PE4 PE3 PE2 PE1 PE0 • PCINT7 – Port E, Bit 7 ...

Page 82

XCK/AIN0/PCINT2 – Port E, Bit 2 XCK, USART External Clock. The Data Direction Register (DDE2) controls whether the clock is output (DDE2 set) or input (DDE2 cleared). The XCK pin is active only when the USART oper- ates in ...

Page 83

Table 13-17. Overriding Signals for Alternate Functions in PE3:PE0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO Note: 13.3.6 Alternate Functions of Port F The Port F has an alternate function as analog input for ...

Page 84

TDO, ADC6 – Port F, Bit 6 ADC6, Analog to Digital Converter, Channel 6 TDO, JTAG Test Data Out: Serial output data from Instruction Register or Data Register. When the JTAG interface is enabled, this pin can not be ...

Page 85

Table 13-20. Overriding Signals for Alternate Functions in PF3:PF0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 13.3.7 Alternate Functions of Port G The alternate pin configuration is as follows: Table 13-21. Port G Pins ...

Page 86

SEG4 – Port G, Bit 2 SEG4, LCD front plane 4 • SEG13 – Port G, Bit 1 SEG13, Segment driver 13 • SEG14 – Port G, Bit 0 SEG14, LCD front plane 14 Table 13-21 on page 85 ...

Page 87

Table 13-23. Overriding Signals for Alternate Functions in PG3:0 Signal Name PUOE PUOV DDOE DDOV PVOE PVOV PTOE DIEOE DIEOV DI AIO 8018P–AVR–08/10 PG3/T1/SEG24 PG2/SEG4 LCDEN • LCDEN (LCDPM> LCDEN • LCDEN (LCDPM> ...

Page 88

Register Description for I/O-Ports 13.4.1 MCUCR – MCU Control Register Bit 0x35 (0x55) Read/Write Initial Value • Bit 4 – PUD: Pull-up Disable When this bit is written to one, the pull-ups in the I/O ports are disabled even ...

Page 89

PORTC – Port C Data Register Bit 0x08 (0x28) Read/Write Initial Value 13.4.9 DDRC – Port C Data Direction Register Bit 0x07 (0x27) Read/Write Initial Value 13.4.10 PINC – Port C Input Pins Address Bit 0x06 (0x26) Read/Write Initial ...

Page 90

PINE – Port E Input Pins Address Bit 0x0C (0x2C) Read/Write Initial Value 13.4.17 PORTF – Port F Data Register Bit 0x11 (0x31) Read/Write Initial Value 13.4.18 DDRF – Port F Data Direction Register Bit 0x10 (0x30) Read/Write Initial ...

Page 91

Timer/Counter0 with PWM 14.1 Features • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct Pulse Width Modulator (PWM) • Frequency Generator • External Event Counter • 10-bit Clock Prescaler • ...

Page 92

The double buffered Output Compare Register (OCR0A) is compared with the Timer/Counter value at all times. The result of the compare can be used by the Waveform Generator to gener- ate a PWM or variable frequency output on the Output ...

Page 93

Signal description (internal signals): count direction clear clk top bottom Depending of the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select bits (CS02:0). When no clock source ...

Page 94

Figure 14-3. Output Compare Unit, Block Diagram The OCR0A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the normal and Clear Timer on Compare (CTC) modes of operation, the double buff- ering is ...

Page 95

Using the Output Compare Unit Since writing TCNT0 in any mode of operation will block all compare matches for one timer clock cycle, there are risks involved when changing TCNT0 when using the Output Compare unit, independently of whether ...

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The design of the Output Compare pin logic allows initialization of the OC0A state before the output is enabled. Note that some COM0A1:0 bit settings are reserved for certain modes of operation. 14.6.1 Compare Output Mode and Waveform Generation The ...

Page 97

The timing diagram for the CTC mode is shown in increases until a compare match occurs between TCNT0 and OCR0A, and then counter (TCNT0) is cleared. Figure 14-5. CTC Mode, Timing Diagram TCNTn OCn (Toggle) Period An interrupt can be ...

Page 98

In fast PWM mode, the counter is incremented until the counter value matches the MAX value. The counter is then cleared at the following timer clock cycle. The timing diagram for the fast PWM mode is shown in togram for ...

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OC0A toggle in CTC mode, except the double buffer feature of the Out- put Compare unit is enabled in the fast PWM mode. 14.7.4 Phase Correct PWM Mode The phase correct PWM mode (WGM01:0 = ...

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The PWM waveform is generated by clearing (or setting) the OC0A Register at the compare match between OCR0A and TCNT0 when the counter increments, and setting (or clearing) the OC0A Register at compare match between OCR0A and ...

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Figure 14-9. Timer/Counter Timing Diagram, with Prescaler (f clk clk (clk TCNTn TOVn Figure 14-10 Figure 14-10. Timer/Counter Timing Diagram, Setting of OCF0A, with Prescaler (f clk clk (clk TCNTn OCRnx OCFnx Figure 14-11 Figure 14-11. Timer/Counter Timing Diagram, Clear ...

Page 102

Timer/Counter Register Description 14.9.1 TCCR0A – Timer/Counter Control Register A Bit 0x24 (0x44) Read/Write Initial Value • Bit 7 – FOC0A: Force Output Compare A The FOC0A bit is only active when the WGM00 bit specifies a non-PWM ...

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When OC0A is connected to the pin, the function of the COM0A1:0 bits depends on the WGM01:0 bit setting. are set to a normal or CTC mode (non-PWM). Table 14-3. COM0A1 Table 14-4 mode. Table 14-4. ...

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Table 14-6. CS02 external pin modes are used for the Timer/Counter0, transitions on the T0 pin will clock the counter even if the pin is configured as an output. This feature ...

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Bit 1 – OCIE0A: Timer/Counter0 Output Compare Match A Interrupt Enable When the OCIE0A bit is written to one, and the I-bit in the Status Register is set (one), the Timer/Counter0 Compare Match A interrupt is enabled. The corresponding ...

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Timer/Counter1 15.1 Features • True 16-bit Design (that is, allows 16-bit PWM) • Two independent Output Compare Units • Double Buffered Output Compare Registers • One Input Capture Unit • Input Capture Noise Canceler • Clear Timer on ...

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Figure 15-1. 16-bit Timer/Counter Block Diagram Note: 15.2.1 Registers The Timer/Counter (TCNT1), Output Compare Registers (OCR1A/B), and Input Capture Regis- ter (ICR1) are all 16-bit registers. Special procedures must be followed when accessing the 16- bit registers. These procedures are ...

Page 108

Compare Units” on page 115. Flag (OCF1A/B) which can be used to generate an Output Compare interrupt request. The Input Capture Register can capture the Timer/Counter value at a given external (edge trig- gered) event on either the Input ...

Page 109

Accessing 16-bit Registers The TCNT1, OCR1A/B, and ICR1 are 16-bit registers that can be accessed by the AVR CPU via the 8-bit data bus. The 16-bit register must be byte accessed using two read or write operations. Each 16-bit ...

Page 110

The following code examples show how atomic read of the TCNT1 Register contents. Reading any ...

Page 111

The following code examples show how atomic write of the TCNT1 Register contents. Writing any of the OCR1A/B or ICR1 Registers can be done by using the same principle. Assembly Code Example TIM16_WriteTCNT1: C Code Example void ...

Page 112

Counter Unit The main part of the 16-bit Timer/Counter is the programmable 16-bit bi-directional counter unit. Figure 15-2 Figure 15-2. Counter Unit Block Diagram Signal description (internal signals): Count Direction Clear clk TOP BOTTOM The 16-bit counter is mapped ...

Page 113

The Timer/Counter Overflow Flag (TOV1) is set according to the mode of operation selected by the WGM13:0 bits. TOV1 can be used for generating a CPU interrupt. 15.6 Input Capture Unit The Timer/Counter incorporates an Input Capture unit that can ...

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TOP value can be written to the ICR1 Register. When writing the ICR1 Register the high byte must be written to the ICR1H I/O location before the low byte is written ...

Page 115

I/O bit location). For measuring frequency only, the clearing of the ICF1 Flag is not required (if an interrupt handler is used). 15.7 Output Compare Units The 16-bit comparator continuously compares ...

Page 116

PWM pulses, thereby making the out- put glitch-free. The OCR1x Register access may seem complex, but this is not case. When the double buffering is enabled, the CPU has access to the OCR1x Buffer ...

Page 117

Compare Match Output Unit The Compare Output mode (COM1x1:0) bits have two functions. The Waveform Generator uses the COM1x1:0 bits for defining the Output Compare (OC1x) state at the next compare match. Secondly the COM1x1:0 bits control the OC1x ...

Page 118

Compare Output Mode and Waveform Generation The Waveform Generator uses the COM1x1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM1x1 tells the Waveform Generator that no action on the OC1x Register ...

Page 119

The timing diagram for the CTC mode is shown in increases until a compare match occurs with either OCR1A or ICR1, and then counter (TCNT1) is cleared. Figure 15-6. CTC Mode, Timing Diagram TCNTn OCnA (Toggle) Period An interrupt can ...

Page 120

Fast PWM Mode The fast Pulse Width Modulation or fast PWM mode (WGM13 14, or 15) provides a high frequency PWM waveform generation option. The fast PWM differs from the other PWM options by its ...

Page 121

ICR1 is used for defining the TOP value. If one of the interrupts are enabled, the interrupt han- dler routine can be used for updating the TOP and compare values. When changing the TOP value the program must ensure ...

Page 122

Phase Correct PWM Mode The phase correct Pulse Width Modulation or phase correct PWM mode (WGM13 10, or 11) provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is, ...

Page 123

The Timer/Counter Overflow Flag (TOV1) is set each time the counter reaches BOTTOM. When either OCR1A or ICR1 is used for defining the TOP value, the OC1A or ICF1 Flag is set accord- ingly at the same timer clock cycle ...

Page 124

Phase and Frequency Correct PWM Mode The phase and frequency correct Pulse Width Modulation, or phase and frequency correct PWM mode (WGM13 provides a high resolution phase and frequency correct PWM wave- form generation option. ...

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Figure 15-9. Phase and Frequency Correct PWM Mode, Timing Diagram TCNTn OCnx OCnx Period The Timer/Counter Overflow Flag (TOV1) is set at the same timer clock cycle as the OCR1x Registers are updated with the double buffer value (at BOTTOM). ...

Page 126

The extreme values for the OCR1x Register represents special cases when generating a PWM waveform output in the phase and frequency correct PWM mode. If the OCR1x is set equal to BOTTOM the output will be continuously low and if ...

Page 127

BOTTOM+1 and so on. The same renaming applies for modes that set the TOV1 Flag at BOTTOM. Figure 15-12. Timer/Counter Timing Diagram, no Prescaling (PC and PFC PWM) Figure 15-13 Figure 15-13. Timer/Counter Timing Diagram, with Prescaler (f and ICF ...

Page 128

Timer/Counter Register Description 15.11.1 TCCR1A – Timer/Counter1 Control Register A Bit (0x80) Read/Write Initial Value • Bit 7:6 – COM1A1:0: Compare Output Mode for Unit A • Bit 5:4 – COM1B1:0: Compare Output Mode for Unit B The ...

Page 129

Table 15-3 correct or the phase and frequency correct, PWM mode. Table 15-3. COM1A1/COM1B1 Note: • Bit 1:0 – WGM11:0: Waveform Generation Mode Combined with the WGM13:2 bits found in the TCCR1B Register, these bits control the counting sequence of ...

Page 130

Table 15-4. Waveform Generation Mode Bit Description WGM12 WGM11 Mode WGM13 (CTC1) (PWM11 ...

Page 131

When a capture is triggered according to the ICES1 setting, the counter value is copied into the Input Capture Register (ICR1). The event will also set the Input Capture Flag (ICF1), and this can be used to cause an Input ...

Page 132

FOC1A/FOC1B bits are implemented as strobes. Therefore it is the value present in the COM1x1:0 bits that determine the effect of the forced compare. A FOC1A/FOC1B strobe will not generate any interrupt nor will it clear the timer in Clear ...

Page 133

ICR1H and ICR1L – Input Capture Register 1 Bit (0x87) (0x86) Read/Write Initial Value The Input Capture is updated with the counter (TCNT1) value each time an event occurs on the ICP1 pin (or optionally on the Analog Comparator ...

Page 134

TIFR1 – Timer/Counter1 Interrupt Flag Register Bit 0x16 (0x36) Read/Write Initial Value • Bit 5 – ICF1: Timer/Counter1, Input Capture Flag This flag is set when a capture event occurs on the ICP1 pin. When the Input Capture Register ...

Page 135

Timer/Counter0 and Timer/Counter1 Prescalers Timer/Counter1 and Timer/Counter0 share the same prescaler module, but the Timer/Counters can have different prescaler settings. The description below applies to both Timer/Counter1 and Timer/Counter0. 16.1 Prescaler Reset The prescaler is free running, that is, ...

Page 136

Enabling and disabling of the clock input must be done when T1/T0 has been stable for at least one system clock cycle, otherwise risk that a false Timer/Counter clock pulse is generated. Each half period of the ...

Page 137

Register Description 16.4.1 GTCCR – General Timer/Counter Control Register Bit 0x23 (0x43) Read/Write Initial Value • Bit 7 – TSM: Timer/Counter Synchronization Mode Writing the TSM bit to one activates the Timer/Counter Synchronization mode. In this mode, the value ...

Page 138

Timer/Counter2 with PWM and Asynchronous Operation Timer/Counter2 is a general purpose, single compare unit, 8-bit Timer/Counter module. The main features are: • Single Compare Unit Counter • Clear Timer on Compare Match (Auto Reload) • Glitch-free, Phase Correct ...

Page 139

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK2). TIFR2 and TIMSK2 are not shown in the figure. The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from the TOSC1/2 pins, as detailed ...

Page 140

Figure 17-2. Counter Unit Block Diagram Signal description (internal signals): count direction clear clk top bottom Depending on the mode of operation used, the counter is cleared, incremented, or decremented at each timer clock (clk selected by the Clock Select ...

Page 141

Figure 17-3. Output Compare Unit, Block Diagram The OCR2A Register is double buffered when using any of the Pulse Width Modulation (PWM) modes. For the Normal and Clear Timer on Compare (CTC) modes of operation, the double buffering is disabled. ...

Page 142

The setup of the OC2A should be performed before setting the Data Direction Register for the port pin to output. The easiest way of setting the OC2A value is to use the Force Output Com- pare (FOC2A) strobe bit in ...

Page 143

Compare Output Mode and Waveform Generation The Waveform Generator uses the COM2A1:0 bits differently in normal, CTC, and PWM modes. For all modes, setting the COM2A1 tells the Waveform Generator that no action on the OC2A Register ...

Page 144

Figure 17-5. CTC Mode, Timing Diagram TCNTn OCnx (Toggle) Period An interrupt can be generated each time the counter value reaches the TOP value by using the OCF2A Flag. If the interrupt is enabled, the interrupt handler routine can be ...

Page 145

PWM mode is shown in togram for illustrating the single-slope operation. The diagram includes non-inverted and inverted PWM outputs. The small horizontal line marks on the TCNT2 slopes represent compare matches between OCR2A and TCNT2. Figure 17-6. Fast PWM Mode, ...

Page 146

Phase Correct PWM Mode The phase correct PWM mode (WGM21 provides a high resolution phase correct PWM waveform generation option. The phase correct PWM mode is based on a dual-slope operation. The counter counts repeatedly from BOTTOM ...

Page 147

OC2A Register at compare match between OCR2A and TCNT2 when the counter decrements. The PWM frequency for the output when using phase correct PWM can be calcu- lated by the following equation: The N variable represents the prescale ...

Page 148

Timer/Counter Timing Diagrams The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk is therefore shown as a clock enable signal. In asynchronous mode, clk the Timer/Counter Oscillator clock. The figures include information on when ...

Page 149

Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2A, with Prescaler (f Figure 17-11 Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match mode, with Pres- 8018P–AVR–08/10 clk I/O clk Tn (clk /8) I/O TCNTn OCRnx - 1 OCRnx OCFnx ...

Page 150

Asynchronous operation of the Timer/Counter 17.8.1 Asynchronous Operation of Timer/Counter2 When Timer/Counter2 operates asynchronously, some considerations must be taken. • Warning: When switching between asynchronous and synchronous clocking of Timer/Counter2, the Timer Registers TCNT2, OCR2A, and TCCR2A might be ...

Page 151

Power-down or Standby mode due to unstable clock signal upon start-up, no matter whether the Oscillator is in use or a clock signal is applied to the TOSC1 pin. • Description of wake up from Power-save or ADC Noise ...

Page 152

Timer/Counter Prescaler Figure 17-12. Prescaler for Timer/Counter2 TOSC1 The clock source for Timer/Counter2 is named clk system I/O clock clk clocked from the TOSC1 pin. This enables use of Timer/Counter2 as a Real Time Counter (RTC). When AS2 is ...

Page 153

Timer/Counter Register Description 17.10.1 TCCR2A – Timer/Counter Control Register A Bit (0xB0) Read/Write Initial Value • Bit 7 – FOC2A: Force Output Compare A The FOC2A bit is only active when the WGM bits specify a non-PWM mode. ...

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Table 17-3. COM2A1 Table 17-4 mode. Table 17-4. COM2A1 Note: Table 17-5 rect PWM mode. Table 17-5. COM2A1 Note: 8018P–AVR–08/10 Compare Output Mode, non-PWM Mode COM2A0 Description 0 0 Normal port operation, ...

Page 155

Bit 2:0 – CS22:0: Clock Select The three Clock Select bits select the clock source to be used by the Timer/Counter, see 17-6. Table 17-6. CS22 17.10.2 TCNT2 – Timer/Counter Register ...

Page 156

TIMSK2 – Timer/Counter2 Interrupt Mask Register Bit (0x70) Read/Write Initial Value • Bit 1 – OCIE2A: Timer/Counter2 Output Compare Match A Interrupt Enable When the OCIE2A bit is written to one and the I-bit in the Status Register is ...

Page 157

Writing to EXCLK should be done before asynchronous operation is selected. Note that the crystal Oscillator will only run when this bit is zero. • Bit 3 – AS2: Asynchronous Timer/Counter2 When AS2 is written to zero, ...

Page 158

SPI – Serial Peripheral Interface 18.1 Features • Full-duplex, Three-wire Synchronous Data Transfer • Master or Slave Operation • LSB First or MSB First Data Transfer • Seven Programmable Bit Rates • End of Transmission Interrupt Flag • Write ...

Page 159

The interconnection between Master and Slave CPUs with SPI is shown in tem consists of two shift Registers, and a Master clock generator. The SPI Master initiates the communication cycle when pulling low the Slave Select SS pin of the ...

Page 160

When the SPI is enabled, the data direction of the MOSI, MISO, SCK, and SS pins is overridden according to Functions” on page Table 18-1. Pin MOSI MISO SCK SS Note: The following code examples show how to initialize the ...

Page 161

Assembly Code Example SPI_MasterInit: SPI_MasterTransmit: Wait_Transmit: C Code Example void SPI_MasterInit(void void SPI_MasterTransmit(char cData Note: 8018P–AVR–08/10 (1) ; Set MOSI and SCK output, all others input ldi r17,(1<<DD_MOSI)|(1<<DD_SCK) out DDR_SPI,r17 ; Enable SPI, Master, set clock ...

Page 162

The following code examples show how to initialize the SPI as a Slave and how to perform a simple reception. Assembly Code Example SPI_SlaveInit: SPI_SlaveReceive: C Code Example void SPI_SlaveInit(void char SPI_SlaveReceive(void Note: 8018P–AVR–08/10 (1) ; ...

Page 163

SS Pin Functionality 18.3.1 Slave Mode When the SPI is configured as a Slave, the Slave Select (SS) pin is always input. When SS is held low, the SPI is activated, and MISO becomes an output if configured so ...

Page 164

Data Modes There are four combinations of SCK phase and polarity with respect to serial data, which are determined by control bits CPHA and CPOL. The SPI data transfer formats are shown in 18-3 and nal, ensuring sufficient time ...

Page 165

Register Description 18.5.1 SPCR – SPI Control Register Bit 0x2C (0x4C) Read/Write Initial Value • Bit 7 – SPIE: SPI Interrupt Enable This bit causes the SPI interrupt to be executed if SPIF bit in the SPSR Register is ...

Page 166

Bits 1, 0 – SPR1, SPR0: SPI Clock Rate Select 1 and 0 These two bits control the SCK rate of the device configured as a Master. SPR1 and SPR0 have no effect on the Slave. The relationship between ...

Page 167

SPDR – SPI Data Register Bit 0x2E (0x4E) Read/Write Initial Value The SPI Data Register is a read/write register used for data transfer between the Register File and the SPI Shift Register. Writing to the register initiates data transmission. ...

Page 168

USART 19.1 Features • Full Duplex Operation (Independent Serial Receive and Transmit Registers) • Asynchronous or Synchronous Operation • Master or Slave Clocked Synchronous Operation • High Resolution Baud Rate Generator • Supports Serial Frames with ...

Page 169

Figure 19-1. USART Block Diagram Note: The dashed boxes in the block diagram separate the three main parts of the USART (listed from the top): Clock Generator, Transmitter and Receiver. Control Registers are shared by all units. The Clock Generation ...

Page 170

AVR USART vs. AVR UART – Compatibility The USART is fully compatible with the AVR UART regarding: • Bit locations inside all USART Registers. • Baud Rate Generation. • Transmitter Operation. • Transmit Buffer Functionality. • Receiver Operation. However, ...

Page 171

Figure 19-2. Clock Generation Logic, Block Diagram Signal description: txclk rxclk xcki xcko fosc 19.3.1 Internal Clock Generation – The Baud Rate Generator Internal clock generation is used for the asynchronous and the synchronous master modes of operation. The description ...

Page 172

Table 19-1. Operating Mode Asynchronous Normal mode (U2Xn = 0) Asynchronous Double Speed mode (U2Xn = 1) Synchronous Master mode Note: BAUD f OSC UBRRn Some examples of UBRRn values for some system clock frequencies are found in page 190. ...

Page 173

Synchronous Clock Operation When synchronous mode is used (UMSELn = 1), the XCK pin will be used as either clock input (Slave) or clock output (Master). The dependency between the clock edges and data sampling or data change is ...

Page 174

Figure 19-4. Frame Formats St ( IDLE The frame format used by the USART is set by the UCSZn2:0, UPM1n:0 and USBSn bits in UCSRnB and UCSRnC. The Receiver and Transmitter use the same setting. Note that changing ...

Page 175

USART Initialization The USART has to be initialized before any communication can take place. The initialization pro- cess normally consists of setting the baud rate, setting frame format and enabling the Transmitter or the Receiver depending on the usage. ...

Page 176

For the assembly code, the baud rate parameter is assumed to be stored in the r17:r16 Registers. Assembly Code Example USART_Init: C Code Example #define FOSC 1843200// Clock Speed #define BAUD 9600 #define MYUBRR FOSC/16/BAUD-1 void main( void ) { ...

Page 177

Data Transmission – The USART Transmitter The USART Transmitter is enabled by setting the Transmit Enable (TXENn) bit in the UCSRnB Register. When the Transmitter is enabled, the normal port operation of the TxD pin is overrid- den by ...

Page 178

Sending Frames with 9 Data Bit If 9-bit characters are used (UCSZ = 7), the ninth bit must be written to the TXB8n bit in UCSRnB before the low byte of the character is written to UDRn. The following ...

Page 179

Transmitter Flags and Interrupts The USART Transmitter has two flags that indicate its state: USART Data Register Empty (UDREn) and Transmit Complete (TXCn). Both flags can be used for generating interrupts. The Data Register Empty (UDREn) Flag indicates whether ...

Page 180

Data Reception – The USART Receiver The USART Receiver is enabled by writing the Receive Enable (RXENn) bit in the UCSRnB Register to one. When the Receiver is enabled, the normal pin operation of the RxD pin is over- ...

Page 181

Receiving Frames with 9 Data Bits If 9-bit characters are used (UCSZ=7) the ninth bit must be read from the RXB8n bit in UCSRnB before reading the low bits from the UDRn. This rule applies to the FEn, DORn ...

Page 182

Assembly Code Example USART_Receive: USART_ReceiveNoError: C Code Example unsigned int USART_Receive( void ) { } Note: The receive function example reads all the I/O Registers into the Register File before any com- putation is done. This gives an optimal receive ...

Page 183

Receive Compete Flag and Interrupt The USART Receiver has one flag that indicates the Receiver state. The Receive Complete (RXCn) Flag indicates if there are unread data present in the receive buf- fer. This flag is one when unread ...

Page 184

Parity Checker The Parity Checker is active when the high USART Parity mode (UPM1n) bit is set. Type of Par- ity Check to be performed (odd or even) is selected by the UPM0n bit. When enabled, the Parity Checker ...

Page 185

Asynchronous Data Reception The USART includes a clock recovery and a data recovery unit for handling asynchronous data reception. The clock recovery logic is used for synchronizing the internally generated baud rate clock to the incoming asynchronous serial frames ...

Page 186

Figure 19-6. Sampling of Data and Parity Bit The decision of the logic level of the received bit is taken by doing a majority voting of the logic value to the three samples in the center of the received bit. ...

Page 187

The following equations can be used to calculate the ratio of the incoming data rate and internal receiver baud rate slow Table 19-2 that Normal Speed mode has higher toleration of baud rate ...

Page 188

The recommendations of the maximum receiver baud rate error was made under the assump- tion that the Receiver and Transmitter equally divides the maximum total error. There are two possible sources for the receivers baud rate error. The Receiver’s system ...

Page 189

When the last data frame is received by the addressed MCU, the addressed MCU sets the MPCMn bit and waits for a new address frame from master. The process then repeats from 2. Using any of the 5-bit to ...

Page 190

Examples of Baud Rate Setting For standard crystal and resonator frequencies, the most commonly used baud rates for asyn- chronous operation can be generated by using the UBRRn settings in values which yield an actual baud rate differing less ...

Page 191

Table 19-5. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 3.6864 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 95 0.0% 191 4800 47 0.0% 95 9600 23 0.0% ...

Page 192

Table 19-6. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 8.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 207 0.2% 416 4800 103 0.2% 207 9600 51 0.2% ...

Page 193

Table 19-7. Examples of UBRRn Settings for Commonly Used Oscillator Frequencies (Continued 16.0000 MHz osc Baud U2Xn = 0 U2Xn = 1 Rate (bps) UBRRn Error UBRRn 2400 416 -0.1% 832 4800 207 0.2% 416 9600 103 0.2% ...

Page 194

USART Register Description 19.11.1 UDRn – USART I/O Data Register Bit (0xC6) Read/Write Initial Value The USART Transmit Data Buffer Register and USART Receive Data Buffer Registers share the same I/O address referred to as USART Data Register or ...

Page 195

UDREn is set after a reset to indicate that the Transmitter is ready. • Bit 4 – FEn: Frame Error n This bit is set if the next character in the receive buffer had a Frame Error when received, that ...

Page 196

Bit 5 – UDRIEn: USART Data Register Empty Interrupt Enable Writing this bit to one enables interrupt on the UDREn Flag. A Data Register Empty interrupt will be generated only if the UDRIEn bit is written to one, the ...

Page 197

Receiver will generate a parity value for the incoming data and compare it to the UPM0n setting mismatch is detected, the UPEn Flag in UCSRnA will be set. Table 19-9. • Bit 3 – USBSn: Stop Bit Select ...

Page 198

UBRRLn and UBRRHn – USART Baud Rate Registers Bit (0xC5) (0xC4) Read/Write Initial Value • Bit 15:12 – Reserved Bits These bits are reserved for future use. For compatibility with future devices, these bit must be written to zero ...

Page 199

USI – Universal Serial Interface The Universal Serial Interface, or USI, provides the basic hardware resources needed for serial communication. Combined with a minimum of control software, the USI allows significantly higher transfer rates and uses less code space ...

Page 200

Note that when an external clock source is selected the counter counts both clock edges. In this case the counter counts the number of edges, and not the number of bits. The clock ...

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