DSPIC33FJ32GP302-I/SP Microchip Technology, DSPIC33FJ32GP302-I/SP Datasheet - Page 50

• Manufacturer Part Number: DSPIC33FJ32GP302-I/SP
• Description: IC DSPIC MCU/DSP 32K 28SPDIP
• Manufacturer: Microchip Technology
• Series: dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP302-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 32KB (32K x 8)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: dsPIC
• Core Size: 16-Bit
• Speed: 40 MIPs
• Connectivity: I²C, IrDA, LIN, SPI, UART/USART
• Peripherals: AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
• Number Of I /o: 21
• Ram Size: 4K x 8
• Voltage - Supply (vcc/vdd): 3 V ~ 3.6 V
• Data Converters: A/D 10x10b/12b
• Oscillator Type: Internal
• Operating Temperature: -40°C ~ 85°C
• Product: DSCs
• Data Bus Width: 16 bit
• Processor Series: DSPIC33F
• Core: dsPIC
• Maximum Clock Frequency: 40 MHz
• Number Of Programmable I/os: 21
• Data Ram Size: 4 KB
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52713-733, 52714-737, 53276-922, EWDSPIC
• Development Tools By Supplier: PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
• Minimum Operating Temperature: - 40 C
• Package: 28SPDIP
• Device Core: dsPIC
• Family Name: dSPIC33
• Maximum Speed: 40 MHz
• Operating Supply Voltage: 3.3 V
• Interface Type: I2C/SPI/UART
• On-chip Adc: 10-chx10-bit|10-chx12-bit
• Number Of Timers: 3
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

dsPIC33FJ32GP202/204 and dsPIC33FJ16GP304
4.4.3
Modulo Addressing can be applied to the Effective
Address (EA) calculation associated with any W
register.
Address boundaries check for addresses equal to:
• The upper boundary addresses for incrementing
• The lower boundary addresses for decrementing
It is important to realize that the address boundaries
also check for addresses less than or greater than
these addresses. Address changes can, therefore,
jump beyond boundaries and still be adjusted correctly.
4.5
Bit-Reversed Addressing mode is intended to simplify
data re-ordering for radix-2 FFT algorithms. It is
supported by the X AGU for data writes only.
The modifier, which can be a constant value or register
contents, is regarded as having its bit order reversed. The
address source and destination are kept in normal order.
Thus, the only operand requiring reversal is the modifier.
4.5.1
Bit-Reversed Addressing mode is enabled in any of
these situations:
• BWM bits (W register selection) in the MODCON
• The BREN bit is set in the XBREV register.
• The addressing mode used is Register Indirect
DS70290F-page 50
buffers
buffers
Note:
register are any value other than ‘15’ (the stack
cannot be accessed using Bit-Reversed
Addressing).
with Pre-Increment or Post-Increment.
Bit-Reversed Addressing
MODULO ADDRESSING
APPLICABILITY
The modulo corrected effective address is
written back to the register only when
Pre-Modify or Post-Modify Addressing
mode is used to compute the effective
address. When an address offset (such as
[W7+W2]) is used, Modulo Address
correction is performed but the contents of
the register remain unchanged.
BIT-REVERSED ADDRESSING
IMPLEMENTATION
Preliminary
If the length of a bit-reversed buffer is M = 2
the last ‘N’ bits of the data buffer start address must
be zeros.
XB<14:0> is the Bit-Reversed Address modifier, or
‘pivot point’, which is typically a constant. In the case of
an FFT computation, its value is equal to half of the FFT
data buffer size.
When enabled, Bit-Reversed Addressing is executed
only for Register Indirect with Pre-Increment or
Post-Increment Addressing and word sized data writes.
It will not function for any other addressing mode or for
byte sized data, and normal addresses are generated
instead. When Bit-Reversed Addressing is active, the
W Address Pointer is always added to the address
modifier (XB), and the offset associated with the Regis-
ter Indirect Addressing mode is ignored. In addition, as
word sized data is a requirement, the LSb of the EA is
ignored (and always clear).
If Bit-Reversed Addressing has already been enabled
by setting the BREN (XBREV<15>) bit, a write to the
XBREV register should not be immediately followed by
an indirect read operation using the W register that has
been designated as the bit-reversed pointer.
Note:
Note:
All bit-reversed EA calculations assume
word sized data (LSB of every EA is
always clear). The XB value is scaled
accordingly to generate compatible (byte)
addresses.
Modulo Addressing and Bit-Reversed
Addressing
together. If an application attempts to do so,
Bit-Reversed Addressing will assume
priority when active for the X WAGU and X
WAGU
disabled. However, Modulo Addressing will
continue to function in the X RAGU.
Modulo
 2009 Microchip Technology Inc.
should
Addressing
not
be
will
enabled
N
bytes,
be