DSPIC33FJ32GP302-I/SP Microchip Technology, DSPIC33FJ32GP302-I/SP Datasheet - Page 37

IC DSPIC MCU/DSP 32K 28SPDIP

DSPIC33FJ32GP302-I/SP

Manufacturer Part Number
DSPIC33FJ32GP302-I/SP
Description
IC DSPIC MCU/DSP 32K 28SPDIP
Manufacturer
Microchip Technology
Series
dsPIC™ 33Fr

Specifications of DSPIC33FJ32GP302-I/SP

Program Memory Type
FLASH
Program Memory Size
32KB (32K x 8)
Package / Case
28-DIP (0.300", 7.62mm)
Core Processor
dsPIC
Core Size
16-Bit
Speed
40 MIPs
Connectivity
I²C, IrDA, LIN, SPI, UART/USART
Peripherals
AC'97, Brown-out Detect/Reset, DMA, I²S, POR, PWM, WDT
Number Of I /o
21
Ram Size
4K x 8
Voltage - Supply (vcc/vdd)
3 V ~ 3.6 V
Data Converters
A/D 10x10b/12b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Product
DSCs
Data Bus Width
16 bit
Processor Series
DSPIC33F
Core
dsPIC
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
21
Data Ram Size
4 KB
Maximum Operating Temperature
+ 85 C
Mounting Style
Through Hole
3rd Party Development Tools
52713-733, 52714-737, 53276-922, EWDSPIC
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM240001, DV164033
Minimum Operating Temperature
- 40 C
Package
28SPDIP
Device Core
dsPIC
Family Name
dSPIC33
Maximum Speed
40 MHz
Operating Supply Voltage
3.3 V
Interface Type
I2C/SPI/UART
On-chip Adc
10-chx10-bit|10-chx12-bit
Number Of Timers
3
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
DV164033 - KIT START EXPLORER 16 MPLAB ICD2DM240001 - BOARD DEMO PIC24/DSPIC33/PIC32
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
TABLE 4-1:
TABLE 4-2:
TABLE 4-3:
Legend:
CNEN1
CNEN2
CNPU1
CNPU2
Legend:
XMODSRT
XMODEND
YMODSRT
YMODEND
XBREV
DISICNT
Legend:
CNEN1
CNEN2
CNPU1
CNPU2
Name
Name
SFR Name
SFR
SFR
Addr
Addr
006A
0060
0062
0068
006A
0060
0062
0068
SFR
SFR
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
x = unknown value on Reset, — = unimplemented, read as ‘0’. Reset values are shown in hexadecimal.
Addr
004A
004C
004E
0048
0050
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE CN10PUE CN9PUE CN8PUE CN7PUE CN6PUE CN5PUE CN4PUE
SFR
0052
CN15PUE CN14PUE CN13PUE CN12PUE CN11PUE
CN15IE
CN15IE
Bit 15
Bit 15
CPU CORE REGISTERS MAP (CONTINUED)
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GP202
CHANGE NOTIFICATION REGISTER MAP FOR dsPIC33FJ32GP204 AND dsPIC33FJ16GP304
Bit 15
BREN
CN30PUE CN29PUE CN28PUE CN27PUE CN26PUE CN25PUE CN24PUE CN23PUE CN22PUE CN21PUE CN20PUE CN19PUE CN18PUE CN17PUE CN16PUE
CN30PUE CN29PUE
CN14IE
CN30IE
CN14IE
CN30IE
Bit 14
Bit 14
Bit 14
CN13IE
CN29IE
CN13IE
CN29IE
Bit 13
Bit 13
Bit 13
CN12IE
CN12IE
CN28IE
Bit 12
Bit 12
CN27PUE
Bit 12
CN27IE
CN11IE
CN27IE
CN11IE
Bit 11
Bit 11
Bit 11
CN10IE
CN26IE
Bit 10
Bit 10
—-
Bit 10
CN25IE
CN9IE
Bit 9
Bit 9
Bit 9
CN24PUE CN23PUE CN22PUE CN21PUE
CN24IE
CN24IE
CN8IE
Bit 8
Bit 8
XS<15:1>
XE<15:1>
YS<15:1>
YE<15:1>
Bit 8
Disable Interrupts Counter Register
CN7PUE
CN23IE
CN23IE
CN7IE
CN7IE
Bit 7
Bit 7
XB<14:0>
Bit 7
CN6PUE
CN22IE
CN22IE
CN6IE
CN6IE
Bit 6
Bit 6
Bit 6
CN5PUE
CN21IE
CN21IE
CN5IE
CN5IE
Bit 5
Bit 5
Bit 5
CN4PUE
CN20IE
CN4IE
CN4IE
Bit 4
Bit 4
Bit 4
CN3PUE
CN3PUE
CN3IE
CN19IE
Bit 3
CN3IE
Bit 3
Bit 3
CN2PUE
CN2PUE CN1PUE CN0PUE
CN2IE
CN18IE
Bit 2
CN2IE
Bit 2
Bit 2
CN1PUE
CN1IE
CN17IE
Bit 1
CN1IE
Bit 1
Bit 1
CN16PUE
CN0PUE
CN16IE
CN0IE
CN16IE
Bit 0
CN0IE
Bit 0
Bit 0
0
1
0
1
Resets
Resets
0000
0000
0000
0000
0000
0000
0000
0000
Resets
All
All
xxxx
xxxx
xxxx
xxxx
xxxx
xxxx
All

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