PIC18F87J10-I/PT Microchip Technology, PIC18F87J10-I/PT Datasheet - Page 250
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PIC18F87J10-I/PT
Manufacturer Part Number
PIC18F87J10-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F85J10-IPT.pdf
(410 pages)
4.PIC18F85J10-IPT.pdf
(10 pages)
5.PIC18F85J10-IPT.pdf
(10 pages)
6.PIC18F85J10-IPT.pdf
(8 pages)
7.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F87J10-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DV164136, DM183032, DM164120-5
Minimum Operating Temperature
- 40 C
On-chip Adc
15-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Price
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- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F85J10-IPT PDF datasheet #3
- PIC18F85J10-IPT PDF datasheet #4
- PIC18F85J10-IPT PDF datasheet #5
- PIC18F85J10-IPT PDF datasheet #6
- PIC18F66J15-IPT PDF datasheet #7
- Current page: 250 of 400
- Download datasheet (7Mb)
PIC18F87J10
FIGURE 19-7:
TABLE 19-6:
19.2.4
During Sleep mode, all clocks to the EUSART are
suspended. Because of this, the Baud Rate Generator
is inactive and a proper byte reception cannot be per-
formed. The auto-wake-up feature allows the controller
to wake-up due to activity on the RXx/DTx line while the
EUSART is operating in Asynchronous mode.
The auto-wake-up feature is enabled by setting the
WUE bit (BAUDCONx<1>). Once set, the typical
receive sequence on RXx/DTx is disabled and the
EUSART remains in an Idle state, monitoring for a
wake-up event independent of the CPU mode. A
wake-up event consists of a high-to-low transition on
DS39663D-page 248
INTCON
PIR1
PIE1
IPR1
PIR3
PIE3
IPR3
RCSTAx
RCREGx
TXSTAx
BAUDCONx ABDOVF
SPBRGHx
SPBRGx
Legend: — = unimplemented locations read as ‘0’. Shaded cells are not used for asynchronous reception.
Name
Note:
RXx (pin)
Rcv Shift Reg
Rcv Buffer Reg
Read Rcv
Buffer Reg
RCREGx
RCxIF
(Interrupt Flag)
OERR bit
CREN
This timing diagram shows three words appearing on the RXx input. The RCREGx (Receive Buffer) is read after the third word
causing the OERR (Overrun) bit to be set.
AUTO-WAKE-UP ON SYNC BREAK
CHARACTER
EUSARTx Receive Register
EUSARTx Baud Rate Generator Register Low Byte
GIE/GIEH PEIE/GIEL
EUSARTx Baud Rate Generator Register High Byte
SSP2IF
SSP2IE
SSP2IP
PSPIE
PSPIP
PSPIF
CSRC
SPEN
Bit 7
REGISTERS ASSOCIATED WITH ASYNCHRONOUS RECEPTION
ASYNCHRONOUS RECEPTION
Start
bit
BCL2IF
BCL2IE
BCL2IP
bit 0
RCIDL
ADIE
ADIP
Bit 6
ADIF
RX9
TX9
bit 1
TMR0IE
RC1IF
RC1IE
RC1IP
RC2IF
RC2IE
RC2IP
SREN
TXEN
Bit 5
—
bit 7/8
Preliminary
Stop
INT0IE
bit
TX1IF
TX1IE
TX1IP
TX2IF
TX2IE
TX2IP
CREN
SYNC
SCKP
Bit 4
Word 1
RCREGx
Start
bit
TMR4IF
TMR4IE
TMR4IP
bit 0
SSP1IE
SSP1IP
ADDEN
SSP1IF
SENDB
the RXx/DTx line. (This coincides with the start of a
Sync Break or a Wake-up Signal character for the LIN
protocol.)
Following a wake-up event, the module generates an
RCxIF interrupt. The interrupt is generated synchro-
nously to the Q clocks in normal operating modes
(Figure 19-8) and asynchronously if the device is in
Sleep mode (Figure 19-9). The interrupt condition is
cleared by reading the RCREGx register.
The WUE bit is automatically cleared once a
low-to-high transition is observed on the RXx line
following the wake-up event. At this point, the EUSART
module is in Idle mode and returns to normal operation.
This signals to the user that the Sync Break event is
over.
BRG16
RBIE
Bit 3
TMR0IF
CCP1IF
CCP1IE
CCP1IP
CCP5IF
CCP5IE
CCP5IP
bit 7/8
Word 2
RCREGx
BRGH
FERR
Bit 2
—
Stop
bit
TMR2IF
TMR2IE
TMR2IP
CCP4IE
CCP4IP
CCP4IF
INT0IF
OERR
Start
TRMT
© 2006 Microchip Technology Inc.
WUE
Bit 1
bit
TMR1IE
TMR1IP
TMR1IF
CCP3IF
CCP3IE
CCP3IP
ABDEN
RX9D
TX9D
bit 7/8
Bit 0
RBIF
Stop
bit
on page
Values
Reset
49
51
51
51
51
51
51
51
51
51
52
52
52
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