PIC18F87J10-I/PT Microchip Technology, PIC18F87J10-I/PT Datasheet - Page 136
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PIC18F87J10-I/PT
Manufacturer Part Number
PIC18F87J10-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F85J10-IPT.pdf
(410 pages)
4.PIC18F85J10-IPT.pdf
(10 pages)
5.PIC18F85J10-IPT.pdf
(10 pages)
6.PIC18F85J10-IPT.pdf
(8 pages)
7.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F87J10-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DV164136, DM183032, DM164120-5
Minimum Operating Temperature
- 40 C
On-chip Adc
15-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC18F87J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
1 837
Company:
Part Number:
PIC18F87J10-I/PT
Manufacturer:
MICROCHIP
Quantity:
12 000
Company:
Part Number:
PIC18F87J10-I/PT
Manufacturer:
Microchip Technology
Quantity:
10 000
Part Number:
PIC18F87J10-I/PT
Manufacturer:
MICROCHIP/微芯
Quantity:
20 000
- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F85J10-IPT PDF datasheet #3
- PIC18F85J10-IPT PDF datasheet #4
- PIC18F85J10-IPT PDF datasheet #5
- PIC18F85J10-IPT PDF datasheet #6
- PIC18F66J15-IPT PDF datasheet #7
- Current page: 136 of 400
- Download datasheet (7Mb)
PIC18F87J10
TABLE 10-11:
DS39663D-page 134
RE0/AD8/RD/
P2D
RE1/AD9/WR/
P2C
RE2/AD10/CS/
P2B
RE3/AD11/
P3C
RE4/AD12/
P3B
RE5/AD13/
P1C
Legend:
Note 1:
Pin Name
2:
3:
4:
PWR = Power Supply, O = Output, I = Input, ANA = Analog Signal, DIG = Digital Output, ST = Schmitt Buffer Input,
TTL = TTL Buffer Input, x = Don’t care (TRIS bit does not affect port direction or is overridden for this option).
Default assignments for P1B/P1C and P3B/P3C when ECCPMX Configuration bit is set (80-pin devices only).
External memory interface I/O takes priority over all other digital and PSP I/O.
Available on 80-pin devices only.
Alternate assignment for ECCP2/P2A when CCP2MX Configuration bit is cleared (all devices in Microcontroller mode).
Function
AD10
AD12
AD13
AD11
AD8
AD9
P3C
P3B
P1C
PORTE FUNCTIONS
RE0
P2D
RE1
P2C
RE2
P2B
RE3
RE4
RE5
WR
RD
CS
(1)
(3)
(3)
(1)
(1)
(3)
(3)
(3)
(3)
Setting
TRIS
0
1
x
x
1
0
0
1
x
x
1
0
0
1
x
x
1
0
0
1
x
x
0
0
1
x
x
0
0
1
x
x
0
I/O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
I
I
I
I
I
I
I
I
I
I
I
I
I
I
I
Type
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
DIG
DIG
TTL
DIG
I/O
ST
ST
ST
ST
ST
ST
Preliminary
LATE<0> data output.
PORTE<0> data input.
External memory interface, address/data bit 8 output.
External memory interface, data bit 8 input.
Parallel Slave Port read enable control input.
ECCP2 Enhanced PWM output, channel D; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<1> data output.
PORTE<1> data input.
External memory interface, address/data bit 9 output.
External memory interface, data bit 9 input.
Parallel Slave Port write enable control input.
ECCP2 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<2> data output.
PORTE<2> data input.
External memory interface, address/data bit 10 output.
External memory interface, data bit 10 input.
Parallel Slave Port chip select control input.
ECCP2 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<3> data output.
PORTE<3> data input.
External memory interface, address/data bit 11 output.
External memory interface, data bit 11 input.
ECCP3 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<4> data output.
PORTE<4> data input.
External memory interface, address/data bit 12 output.
External memory interface, data bit 12 input.
ECCP3 Enhanced PWM output, channel B; takes priority over port and
PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
LATE<5> data output.
PORTE<5> data input.
External memory interface, address/data bit 13 output.
External memory interface, data bit 13 input.
ECCP1 Enhanced PWM output, channel C; takes priority over port
and PSP data. May be configured for tri-state during Enhanced PWM
shutdown events.
Description
© 2006 Microchip Technology Inc.
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