PIC18F87J10-I/PT Microchip Technology, PIC18F87J10-I/PT Datasheet - Page 204
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PIC18F87J10-I/PT
Manufacturer Part Number
PIC18F87J10-I/PT
Description
IC PIC MCU FLASH 64KX16 80TQFP
Manufacturer
Microchip Technology
Series
PIC® 18Fr
Datasheets
1.PIC16F616T-ISL.pdf
(8 pages)
2.PIC18F63J11-IPT.pdf
(36 pages)
3.PIC18F85J10-IPT.pdf
(410 pages)
4.PIC18F85J10-IPT.pdf
(10 pages)
5.PIC18F85J10-IPT.pdf
(10 pages)
6.PIC18F85J10-IPT.pdf
(8 pages)
7.PIC18F66J15-IPT.pdf
(400 pages)
Specifications of PIC18F87J10-I/PT
Program Memory Type
FLASH
Program Memory Size
128KB (64K x 16)
Package / Case
80-TFQFP
Core Processor
PIC
Core Size
8-Bit
Speed
40MHz
Connectivity
EBI/EMI, I²C, SPI, UART/USART
Peripherals
Brown-out Detect/Reset, POR, PWM, WDT
Number Of I /o
66
Ram Size
3.8K x 8
Voltage - Supply (vcc/vdd)
2 V ~ 3.6 V
Data Converters
A/D 15x10b
Oscillator Type
Internal
Operating Temperature
-40°C ~ 85°C
Processor Series
PIC18F
Core
PIC
Data Bus Width
8 bit
Data Ram Size
3936 B
Interface Type
SPI/I2C/MSSP/EUSART
Maximum Clock Frequency
40 MHz
Number Of Programmable I/os
66
Number Of Timers
5
Maximum Operating Temperature
+ 85 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734, 52712-325, EWPIC18
Development Tools By Supplier
PG164130, DV164035, DV244005, DV164005, PG164120, DM183022, DV164136, DM183032, DM164120-5
Minimum Operating Temperature
- 40 C
On-chip Adc
15-ch x 10-bit
Package
80TQFP
Device Core
PIC
Family Name
PIC18
Maximum Speed
40 MHz
Operating Supply Voltage
2.5|3.3 V
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
MA180015 - MODULE PLUG-IN 18F87J10 FOR HPCAC162062 - HEADER INTRFC MPLAB ICD2 64/80PAC164328 - MODULE SKT FOR 80TQFP
Eeprom Size
-
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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Quantity:
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- PIC16F616T-ISL PDF datasheet
- PIC18F63J11-IPT PDF datasheet #2
- PIC18F85J10-IPT PDF datasheet #3
- PIC18F85J10-IPT PDF datasheet #4
- PIC18F85J10-IPT PDF datasheet #5
- PIC18F85J10-IPT PDF datasheet #6
- PIC18F66J15-IPT PDF datasheet #7
- Current page: 204 of 400
- Download datasheet (7Mb)
PIC18F87J10
REGISTER 18-5:
DS39663D-page 202
bit 7
bit 6
bit 5
bit 4
bit 3
bit 2
bit 1
bit 0
SSPxCON2: MSSPx CONTROL REGISTER 2 (I
bit 7
GCEN: General Call Enable bit (Slave mode only)
1 = Enable interrupt when a general call address (0000h) is received in the SSPxSR
0 = General call address disabled
ACKSTAT: Acknowledge Status bit (Master Transmit mode only)
1 = Acknowledge was not received from slave
0 = Acknowledge was received from slave
ACKDT/ADMSK5: Acknowledge Data bit
In Master Receive mode:
1 = Not Acknowledge
0 = Acknowledge
In Slave mode:
1 = Address masking of ADD5 enabled
0 = Address masking of ADD5 disabled
ACKEN/ADMSK4: Acknowledge Sequence Enable bit
In Master Receive mode:
1 = Initiate Acknowledge sequence on SDAx and SCLx pins and transmit ACKDT data bit. Automatically
0 = Acknowledge sequence Idle
In Slave mode:
1 = Address masking of ADD4 enabled
0 = Address masking of ADD4 disabled
RCEN/ADMSK3: Receive Enable bit
In Master Receive mode:
1 = Enables Receive mode for I
0 = Receive Idle
In Slave mode:
1 = Address masking of ADD3 enabled
0 = Address masking of ADD3 disabled
PEN/ADMSK2: Stop Condition Enable bit
In Master mode:
1 = Initiate Stop condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Stop condition Idle
In Slave mode:
1 = Address masking of ADD2 enabled
0 = Address masking of ADD2 disabled
RSEN/ADMSK1: Repeated Start Condition Enable bit
In Master mode:
1 = Initiate Repeated Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Repeated Start condition Idle
In Slave mode (7-bit Address mode):
1 = Address masking of ADD1 enabled
0 = Address masking of ADD1 disabled
In Slave mode (10-bit Address mode):
1 = Address masking of ADD1 and ADD0 enabled
0 = Address masking of ADD1 and ADD0 disabled
SEN: Start Condition Enable/Stretch Enable bit
In Master mode:
1 = Initiate Start condition on SDAx and SCLx pins. Automatically cleared by hardware.
0 = Start condition Idle
In Slave mode:
1 = Clock stretching is enabled for both slave transmit and slave receive (stretch enabled)
0 = Clock stretching is disabled
Legend:
R = Readable bit
-n = Value at POR
R/W-0
GCEN
Note:
Note 1: For bits ACKEN, RCEN, PEN, RSEN, SEN: If the I
cleared by hardware.
Value that will be transmitted when the user initiates an Acknowledge sequence at the end of
a receive.
(no spooling) and the SSPxBUF may not be written (or writes to the SSPxBUF are disabled).
ACKSTAT
(1)
(1)
R/W-0
(1)
(1)
ADMSK5
ACKDT/
R/W-0
Preliminary
2
C
W = Writable bit
‘1’ = Bit is set
ACKEN
ADMSK4
R/W-0
(1)
(1)
/
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
RCEN
ADMSK3
R/W-0
2
2
C™ MODE)
C module is active, these bits may not be set
(1)
/
ADMSK2
PEN
R/W-0
© 2006 Microchip Technology Inc.
(1)
/
x = Bit is unknown
ADMSK1
RSEN
R/W-0
(1)
/
SEN
R/W-0
(1)
bit 0
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