PIC18F87J10-I/PT Microchip Technology, PIC18F87J10-I/PT Datasheet
PIC18F87J10-I/PT
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PIC18F87J10-I/PT Summary of contents
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... Microchip Technology Inc. PIC18F87J10 64/80-Pin, High-Performance, 1-Mbit Flash Microcontrollers with nanoWatt Technology Preliminary Data Sheet DS39663D ...
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... PowerMate, PowerTool, REAL ICE, rfLAB, rfPICDEM, Select Mode, Smart Serial, SmartTel, Total Endurance, UNI/O, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Secondary oscillator using Timer1 @ 32 kHz • Two-Speed Oscillator Start-up • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops © 2006 Microchip Technology Inc. PIC18F87J10 FAMILY Peripheral Highlights: • High-current sink/source 25 mA/25 mA (PORTB and PORTC) • Four programmable external interrupts • ...
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... PIC18F65J15 48K 24576 PIC18F66J10 64K 32768 PIC18F66J15 96K 49152 PIC18F67J10 128K 65536 PIC18F85J10 32K 16384 PIC18F85J15 48K 24576 PIC18F86J10 64K 32768 PIC18F86J15 96K 49152 PIC18F87J10 128K 65536 Pin Diagrams 64-Pin TQFP 1 RE1/WR/P2C RE0/RD/P2D 2 RG0/ECCP3/P3A 3 RG1/TX2/CK2 4 5 RG2/RX2/DT2 6 RG3/CCP4/P3D 7 MCLR 8 RG4/CCP5/P1D ...
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... RH7/AN15/P1B 19 (2) RH6/AN14/P1C 20 Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode. 2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit. © 2006 Microchip Technology Inc. PIC18F87J10 ...
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... PIC18F87J10 Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Oscillator Configurations ............................................................................................................................................................ 27 3.0 Power-Managed Modes ............................................................................................................................................................. 35 4.0 Reset .......................................................................................................................................................................................... 43 5.0 Memory Organization ................................................................................................................................................................. 55 6.0 Flash Program Memory .............................................................................................................................................................. 81 7.0 External Memory Bus ................................................................................................................................................................. 91 8 Hardware Multiplier.......................................................................................................................................................... 103 9.0 Interrupts .................................................................................................................................................................................. 105 10.0 I/O Ports ................................................................................................................................................................................... 121 11.0 Timer0 Module ......................................................................................................................................................................... 147 12.0 Timer1 Module ......................................................................................................................................................................... 151 13 ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F87J10 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes, using crystals or ceramic resonators. ...
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... Section 26.0 “Electrical Characteristics” for time-out periods. DS39663D-page 6 1.3 Details on Individual Family Members Devices in the PIC18F87J10 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in four ways: 1. ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC18F87J10 FAMILY (64-PIN DEVICES) Features PIC18F65J10 Operating Frequency DC – 40 MHz Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Timers Capture/Compare/PWM Modules Enhanced Capture/ Compare/PWM Modules Serial Communications Parallel Communications (PSP) ...
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... PIC18F87J10 FIGURE 1-1: PIC18F6XJ10/6XJ15 (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (96 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> Instruction Decode and Power-up Timing OSC2/CLKO Generation OSC1/CLKI Oscillator Start-up Timer INTRC Oscillator Power-on Precision ...
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... Power-up 8 Timer Oscillator 8 Start-up Timer ALU<8> Power-on Reset Watchdog Timer Brown-out (2) Reset MCLR DD SS Timer1 Timer2 Timer3 Timer4 CCP4 CCP5 EUSART1 EUSART2 Preliminary PIC18F87J10 PORTA (1) RA0:RA5 PORTB (1) RB0:RB7 4 PORTC Access Bank (1) RC0:RC7 12 PORTD (1) RD0:RD7 PORTE (1) RE0:RE7 8 PORTF PRODL (1) RF1:RF7 8 PORTG 8 8 (1) ...
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... PIC18F87J10 TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP MCLR 7 OSC1/CLKI 39 OSC1 CLKI OSC2/CLKO 40 OSC2 CLKO RA0/AN0 24 RA0 AN0 RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4 27 RA5 AN4 ...
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... In-Circuit Debugger and ICSP™ programming clock pin. I/O TTL Digital I/O. I TTL Interrupt-on-change pin. I/O ST In-Circuit Debugger and ICSP™ programming data pin. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary PIC18F87J10 Description ) DD DS39663D-page 11 ...
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... PIC18F87J10 TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/ECCP2/P2A 29 RC1 T1OSI (1) ECCP2 (1) P2A RC2/ECCP1/P1A 33 RC2 ECCP1 P1A RC3/SCK1/SCL1 34 RC3 SCK1 SCL1 RC4/SDI1/SDA1 35 RC4 SDI1 SDA1 RC5/SDO1 36 RC5 SDO1 RC6/TX1/CK1 31 RC6 TX1 CK1 ...
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... Synchronous serial clock input/output for SPI mode. I/O ST Synchronous serial clock input/output for I I/O ST Digital I/O. I/O TTL Parallel Slave Port data. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary PIC18F87J10 Description 2 C mode DS39663D-page 13 ...
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... PIC18F87J10 TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/RD/P2D 2 RE0 RD P2D RE1/WR/P2C 1 RE1 WR P2C RE2/CS/P2B 64 RE2 CS P2B RE3/P3C 63 RE3 P3C RE4/P3B 62 RE4 P3B RE5/P1C 61 RE5 P1C RE6/P1B 60 RE6 P1B RE7/ECCP2/P2A 59 RE7 (2) ECCP2 (2) P2A Legend: TTL = TTL compatible input ...
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... Digital I/O. I Analog Analog input 10. O — Comparator reference voltage output. I/O ST Digital I/O. I Analog Analog input 11. I/O ST Digital I/O. I TTL SPI slave select input. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary PIC18F87J10 Description ) DD DS39663D-page 15 ...
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... PIC18F87J10 TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/ECCP3/P3A 3 RG0 ECCP3 P3A RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 5 RG2 RX2 DT2 RG3/CCP4/P3D 6 RG3 CCP4 P3D RG4/CCP5/P1D 8 RG4 CCP5 P1D V 9, 25, 41 26, 38 ENVREG DDCORE CAP V DDCORE V CAP ...
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... Digital I/O. I Analog Analog input 3. I Analog A/D reference voltage (high) input. I/O ST Digital I/ Timer0 external clock input. I/O TTL Digital I/O. I Analog Analog input 4. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary PIC18F87J10 Description ) DD DS39663D-page 17 ...
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... PIC18F87J10 TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/FLT0 58 RB0 INT0 FLT0 RB1/INT1 57 RB1 INT1 RB2/INT2 56 RB2 INT2 RB3/INT3/ECCP2/P2A 55 RB3 INT3 (1) ECCP2 (1) P2A RB4/KBI0 54 RB4 KBI0 RB5/KBI1 53 RB5 KBI1 RB6/KBI2/PGC 52 RB6 KBI2 PGC RB7/KBI3/PGD 47 RB7 KBI3 ...
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... EUSART1 asynchronous transmit. I/O ST EUSART1 synchronous clock (see related RX1/DT1). I/O ST Digital I/ EUSART1 asynchronous receive. I/O ST EUSART1 synchronous data (see related TX1/CK1). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary PIC18F87J10 Description 2 C™ mode DS39663D-page 19 ...
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... PIC18F87J10 TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/AD0/PSP0 72 RD0 AD0 PSP0 RD1/AD1/PSP1 69 RD1 AD1 PSP1 RD2/AD2/PSP2 68 RD2 AD2 PSP2 RD3/AD3/PSP3 67 RD3 AD3 PSP3 RD4/AD4/PSP4/SDO2 66 RD4 AD4 PSP4 SDO2 RD5/AD5/PSP5/ 65 SDI2/SDA2 RD5 AD5 PSP5 SDI2 SDA2 ...
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... External memory address/data 14. O — ECCP1 PWM output B. I/O ST Digital I/O. I/O TTL External memory address/data 15. I/O ST Capture 2 input/Compare 2 output/PWM 2 output. O — ECCP2 PWM output A. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary PIC18F87J10 Description ) DD DS39663D-page 21 ...
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... PIC18F87J10 TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF1/AN6/C2OUT 23 RF1 AN6 C2OUT RF2/AN7/C1OUT 18 RF2 AN7 C1OUT RF3/AN8 17 RF3 AN8 RF4/AN9 16 RF4 AN9 RF5/AN10/CV 15 REF RF5 AN10 CV REF RF6/AN11 14 RF6 AN11 RF7/SS1 13 RF7 SS1 Legend: TTL = TTL compatible input ...
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... I/O ST Digital I/O. I/O ST Capture 4 input/Compare 4 output/PWM 4 output. O — ECCP3 PWM output D. I/O ST Digital I/O. I/O ST Capture 5 input/Compare 5 output/PWM 5 output. O — ECCP1 PWM output D. CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary PIC18F87J10 Description ) DD DS39663D-page 23 ...
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... PIC18F87J10 TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RH0/A16 79 RH0 A16 RH1/A17 80 RH1 A17 RH2/A18 1 RH2 A18 RH3/A19 2 RH3 A19 RH4/AN12/P3C 22 RH4 AN12 (5) P3C RH5/AN13/P3B 21 RH5 AN13 (5) P3B RH6/AN14/P1C 20 RH6 AN14 (5) P1C RH7/AN15/P1B 19 RH7 AN15 (5) P1B ...
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... Enable for on-chip voltage regulator. Core logic power or external filter capacitor connection. P — Positive supply for microcontroller core logic (regulator disabled). P — External filter capacitor connection (regulator enabled). CMOS = CMOS compatible input or output Analog = Analog input O = Output OD = Open-Drain (no P diode to V Preliminary PIC18F87J10 Description ) DD DS39663D-page 25 ...
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... PIC18F87J10 NOTES: DS39663D-page 26 Preliminary © 2006 Microchip Technology Inc. ...
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... OSCILLATOR CONFIGURATIONS 2.1 Oscillator Types The PIC18F87J10 family of devices can be operated in five different oscillator modes High-Speed Crystal/Resonator 2. HSPLL High-Speed Crystal/Resonator with Software PLL Control 3. EC External Clock with F OSC 4. ECPLL External Clock with Software PLL Control 5. INTRC Internal 31 kHz Oscillator Four of these are selected by the user by programming the FOSC2:FOSC0 Configuration bits ...
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... OSC2 is not available. FIGURE 2-3: Clock from of external Ext. System Preliminary EXTERNAL CLOCK INPUT OPERATION (EC CONFIGURATION) OSC1/CLKI PIC18F87J10 /4 OSC2/CLKO OSC EXTERNAL CLOCK INPUT OPERATION (HS OSC CONFIGURATION) OSC1 PIC18F87J10 (HS Mode) Open OSC2 © 2006 Microchip Technology Inc. ...
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... OSC1 Mode (1) U-0 U-0 U-0 (1) — — — ( Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 PLL BLOCK DIAGRAM Phase F IN Comparator F OUT Loop Filter 4 VCO SYSCLK U-0 U-0 U-0 — — ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F87J10 family devices are shown in Figure 2-5. See Section 23.0 “Special Features of the CPU” for Configuration register details. ...
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... FOSC2. 2.6.2 OSCILLATOR TRANSITIONS PIC18F87J10 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs dur- ing the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F87J10 REGISTER 2-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 IDLEN bit 7 bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 Unimplemented: Read as ‘0’ bit 3 OSTS: Oscillator Start-up Time-out Status bit 1 = Oscillator Start-up Timer time-out has expired; primary oscillator is running 0 = Oscillator Start-up Timer time-out is running ...
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... Note: See Table 4-2 in Section 4.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2006 Microchip Technology Inc. PIC18F87J10 The second timer is the Oscillator Start-up Timer (OST), intended to keep the chip in Reset until the crystal oscillator is stable (HS modes). The OST does this by counting 1024 oscillator cycles before allowing the oscillator to clock the device ...
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... PIC18F87J10 NOTES: DS39663D-page 34 Preliminary © 2006 Microchip Technology Inc. ...
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... POWER-MANAGED MODES The PIC18F87J10 family devices provide the ability to manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: • ...
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... PIC18F87J10 3.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its ...
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... OSTS bit is set and the primary clock is providing the clock. The IDLEN and SCS bits are not affected by the wake-up; the Timer1 oscillator continues to run n-1 n Clock Transition (1) (1) T PLL 1 2 n-1 n Clock Transition OSTS Bit Set Preliminary PIC18F87J10 DS39663D-page 37 ...
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... PIC18F87J10 3.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times ...
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... RC_RUN mode). The IDLEN and SCS bits are not affected by the wake-up. While in any Idle mode or the Sleep mode, a WDT time-out will result in a WDT wake-up to the Run mode currently specified by the SCS1:SCS0 bits PLL ( OSTS Bit Set Preliminary PIC18F87J10 CSD DS39663D-page 39 ...
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... PIC18F87J10 3.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2006 Microchip Technology Inc. PIC18F87J10 3.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J10 NOTES: DS39663D-page 42 Preliminary © 2006 Microchip Technology Inc. ...
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... RESET The PIC18F87J10 family of devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F87J10 REGISTER 4-1: RCON: RESET CONTROL REGISTER R/W-0 IPEN bit 7 bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘0’ bit 4 RI: RESET Instruction Flag bit 1 = The RESET instruction was not executed (set by firmware only) ...
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... To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. 4.4 Brown-out Reset (BOR) The PIC18F87J10 family of devices incorporate a simple BOR function when the internal regulator is enabled (ENVREG pin is tied Any drop ...
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... Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F87J10 fam- ily devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 4-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2006 Microchip Technology Inc. T PWRT , V RISE > 3. PWRT Preliminary PIC18F87J10 ): CASE PWRT DS39663D-page 47 ...
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... PIC18F87J10 4.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2006 Microchip Technology Inc. PIC18F87J10 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction Stack Resets ...
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... PIC18F87J10 TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F6XJ1X PIC18F8XJ1X POSTINC2 PIC18F6XJ1X PIC18F8XJ1X POSTDEC2 PIC18F6XJ1X PIC18F8XJ1X PREINC2 PIC18F6XJ1X PIC18F8XJ1X PLUSW2 PIC18F6XJ1X PIC18F8XJ1X FSR2H PIC18F6XJ1X PIC18F8XJ1X FSR2L PIC18F6XJ1X PIC18F8XJ1X STATUS PIC18F6XJ1X PIC18F8XJ1X TMR0H PIC18F6XJ1X PIC18F8XJ1X TMR0L PIC18F6XJ1X PIC18F8XJ1X ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2006 Microchip Technology Inc. PIC18F87J10 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction Stack Resets ...
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... PIC18F87J10 TABLE 4-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices TRISJ PIC18F6XJ1X PIC18F8XJ1X TRISH PIC18F6XJ1X PIC18F8XJ1X TRISG PIC18F6XJ1X PIC18F8XJ1X TRISF PIC18F6XJ1X PIC18F8XJ1X TRISE PIC18F6XJ1X PIC18F8XJ1X TRISD PIC18F6XJ1X PIC18F8XJ1X TRISC PIC18F6XJ1X PIC18F8XJ1X TRISB PIC18F6XJ1X PIC18F8XJ1X TRISA PIC18F6XJ1X PIC18F8XJ1X LATJ PIC18F6XJ1X PIC18F8XJ1X ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 4-1 for Reset value for specific condition. © 2006 Microchip Technology Inc. PIC18F87J10 MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction Stack Resets ...
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... PIC18F87J10 NOTES: DS39663D-page 54 Preliminary © 2006 Microchip Technology Inc. ...
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... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The entire PIC18F87J10 family offers a range of on-chip Flash program memory sizes, from 32 Kbytes (up to 16,384 single-word instructions) to 128 Kbytes (65,536 ...
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... Words, CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices in the PIC18F87J10 family are shown in Table 5-1. Their location in the memory map is shown with the other memory vectors in Figure 5-2. Additional details on the device Configuration Words are provided in Section 23.1 “ ...
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... Table 5-2. R/WO-1 R/WO-1 R/WO-1 BW EMB1 EMB0 EASHFT WO = Write-Once bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 U-0 U-0 U-0 — — — bit Bit is unknown DS39663D-page 57 ...
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... In practical terms, this means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 5-3: MEMORY MAPS FOR PIC18F87J10 FAMILY PROGRAM MEMORY MODES (1) Microcontroller Mode Extended Microcontroller Mode On-Chip ...
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... The user must disable the global interrupt enable bits while accessing the stack to prevent inadvertent stack corruption. Return Address Stack <20:0> 11111 11110 11101 00011 Top-of-Stack 001A34h 00010 000D58h 00001 00000 Preliminary PIC18F87J10 Top-of-Stack Access A set of three registers the STKPTR register pushed value by ...
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... PIC18F87J10 5.1.6.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 5-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bits. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
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... IN FAST REGISTER ;STACK SUB1 RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2006 Microchip Technology Inc. PIC18F87J10 5.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... PIC18F87J10 5.2 PIC18 Instruction Cycle 5.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruc- tion register during Q4 ...
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... No, skip this word ; Execute this word as a NOP REG3 ; continue code REG1 ; is RAM location 0? REG1, REG2 ; Yes, execute this word ; 2nd word of instruction REG3 ; continue code Preliminary PIC18F87J10 Word Address 000000h 000002h 000004h 000006h 000008h 00000Ah 00000Ch 00000Eh 000010h 000012h ...
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... PIC18F87J10 5.3 Data Memory Organization Note: The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM ...
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... Unused Read as ‘0’ EFFh F00h Unused F5Fh F60h SFR FFFh Preliminary PIC18F87J10 When The BSR is ignored and the Access Bank is used. The first 96 bytes are general purpose RAM (from Bank 0). The second 160 bytes are Special Function Registers (from Bank 15). ...
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... PIC18F87J10 FIGURE 5-8: DATA MEMORY MAP FOR PIC18FX6J15/X7J10 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 Bank 7 ...
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... This is data RAM which is available for use by all instructions. GPRs start at the bottom of Bank 0 (address 000h) and grow upwards towards the bottom of the SFR area. GPRs are not initialized by a Power-on Reset and are unchanged on all other Resets. Preliminary PIC18F87J10 (2) From Opcode ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 5-3 and Table 5-4. TABLE 5-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J10 FAMILY DEVICES Address Name Address FFFh ...
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... TABLE 5-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) Filename Bit 7 Bit 6 Bit 5 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F87J10 TABLE 5-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Filename Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN — — WDTCON — — — RCON IPEN — — TMR1H Timer1 Register High Byte ...
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... TABLE 5-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Filename Bit 7 Bit 6 Bit 5 TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN RCSTA1 SPEN RX9 SREN EECON2 Program Memory Control Register 2 (not a physical register) EECON1 — — IPR3 SSP2IP BCL2IP RC2IP PIR3 SSP2IF ...
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... PIC18F87J10 TABLE 5-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) Filename Bit 7 Bit 6 Bit 5 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte BAUDCON1 ABDOVF RCIDL — SPBRGH2 EUSART2 Baud Rate Generator Register High Byte BAUDCON2 ABDOVF RCIDL — ECCP1DEL P1RSEN P1DC6 P1DC5 ...
Page 75
... The C and DC bits operate as a borrow and digit borrow bit respectively, in subtraction. U-0 U-0 R/W-x R/W-x — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 R/W-x R/W-x R/W bit Bit is unknown DS39663D-page 73 ...
Page 76
... PIC18F87J10 5.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 5.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
Page 77
... Because Indirect Addressing uses a full 12-bit address, data RAM banking is not necessary. Thus, the current contents of the BSR and the Access RAM bit have no effect on determining the target address. ADDWF, INDF1, 1 FSR1H:FSR1L Preliminary PIC18F87J10 000h Bank 0 100h Bank 1 200h Bank 2 300h 0 Bank 3 through Bank 13 ...
Page 78
... PIC18F87J10 5.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value. They are: • ...
Page 79
... This special addressing mode is known as Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. © 2006 Microchip Technology Inc. PIC18F87J10 When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); ...
Page 80
... PIC18F87J10 FIGURE 5-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh ...
Page 81
... BSR remains unchanged. Direct Addressing, using the BSR to select the data memory bank, operates in the same manner as previously described. Not Accessible Bank 0 Window Bank 1 Bank 2 through Bank 14 Bank 15 SFRs Data Memory Preliminary PIC18F87J10 00h Bank 1 “Window” 5Fh 60h SFRs FFh Access Bank DS39663D-page 79 ...
Page 82
... PIC18F87J10 NOTES: DS39663D-page 80 Preliminary © 2006 Microchip Technology Inc. ...
Page 83
... TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer register points to a byte in program memory. © 2006 Microchip Technology Inc. PIC18F87J10 6.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
Page 84
... PIC18F87J10 FIGURE 6-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 6.5 “Writing to Flash Program Memory”. ...
Page 85
... Value at POR © 2006 Microchip Technology Inc. U-0 U-0 R/W-0 R/W-x — — FREE WRERR W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 R/W-0 R/S-0 U-0 WREN WR — bit Bit is unknown DS39663D-page 83 ...
Page 86
... PIC18F87J10 6.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 6.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
Page 87
... TABLAT. Program Memory (Odd Byte Address) TBLPTR = xxxxx1 TBLRD ; Load TBLPTR with the base ; address of the word ; read into TABLAT and increment ; get data ; read into TABLAT and increment ; get data Preliminary PIC18F87J10 TBLPTR = xxxxx0 TABLAT Read Register DS39663D-page 85 ...
Page 88
... PIC18F87J10 6.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
Page 89
... The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike members of the PIC18F87J10 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten before a programming sequence. ...
Page 90
... PIC18F87J10 EXAMPLE 6-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF INTCON, GIE ...
Page 91
... See Section 23.6 “Program Verification and Code Protection” for details on code protection of Flash program memory. Bit 4 Bit 3 Bit 2 Program Memory Table Pointer Upper Byte (TBLPTR<20:16>) INT0IE RBIE TMR0IF — FREE WRERR WREN Preliminary PIC18F87J10 Reset Bit 1 Bit 0 Values on page INT0IF RBIF — ...
Page 92
... PIC18F87J10 NOTES: DS39663D-page 90 Preliminary © 2006 Microchip Technology Inc. ...
Page 93
... Address Latch Enable (ALE) Control pin 1 Output Enable (OE) Control pin 2 Write Low (WRL) Control pin 3 Write High (WRH) Control pin 4 Byte Address bit 0 (BA0) 5 Chip Enable (CE) Control pin 6 Lower Byte Enable (LB) Control pin 7 Upper Byte Enable (UB) Control pin Preliminary PIC18F87J10 DS39663D-page 91 ...
Page 94
... PIC18F87J10 7.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 7-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions ...
Page 95
... Address and Data Width The PIC18F87J10 family of devices can be indepen- dently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software ...
Page 96
... Resets. 7.5 Program Memory Modes and the External Memory Bus The PIC18F87J10 family of devices are capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the EBDIS bit ...
Page 97
... BYTE WRITE MODE Figure 7-1 shows an example of 16-bit Byte Write mode for PIC18F87J10 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories ...
Page 98
... PIC18F87J10 7.6.2 16-BIT WORD WRITE MODE Figure 7-2 shows an example of 16-bit Word Write mode for PIC18F65J10 devices. This mode is used for word-wide memories which include some of the EPROM and Flash-type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
Page 99
... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2006 Microchip Technology Inc. PIC18F87J10 Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
Page 100
... PIC18F87J10 7.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-4 and Figure 7-5. FIGURE 7-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
Page 101
... This signal only applies to table writes. See Section 6.1 “Table Reads and Table Writes”. © 2006 Microchip Technology Inc. PIC18F87J10 will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
Page 102
... PIC18F87J10 7.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 7-7 and Figure 7-8. FIGURE 7-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
Page 103
... Microchip Technology Inc. PIC18F87J10 In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with ...
Page 104
... PIC18F87J10 NOTES: DS39663D-page 102 Preliminary © 2006 Microchip Technology Inc. ...
Page 105
... Hardware multiply Without hardware multiply signed Hardware multiply Without hardware multiply unsigned Hardware multiply Without hardware multiply signed Hardware multiply © 2006 Microchip Technology Inc. PIC18F87J10 EXAMPLE 8- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 8- SIGNED MULTIPLY ...
Page 106
... PIC18F87J10 Example 8-3 shows the sequence unsigned multiplication. Equation 8-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 8- UNSIGNED MULTIPLICATION ALGORITHM RES3:RES0 = ARG1H:ARG1L ARG2H:ARG2L = (ARG1H ARG2H 2 8 (ARG1H ARG2L 2 8 (ARG1L ARG2H 2 (ARG1L ARG2L) EXAMPLE 8-3: ...
Page 107
... INTERRUPTS Members of the PIC18F87J10 family of devices have multiple interrupt sources and an interrupt priority fea- ture that allows most interrupt sources to be assigned a high priority level or a low priority level. The high priority interrupt vector is at 0008h and the low priority interrupt vector is at 0018h ...
Page 108
... PIC18F87J10 FIGURE 9-1: PIC18F87J10 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<7, 0> PIE3<7, 0> IPR3<7, 0> High Priority Interrupt Generation Low Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<7, 0> ...
Page 109
... This feature allows for software polling. R/W-0 R/W-0 R/W-0 R/W-0 TMR0IE INT0IE RBIE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 R/W-0 R/W-0 R/W-x TMR0IF INT0IF RBIF bit Bit is unknown DS39663D-page 107 ...
Page 110
... PIC18F87J10 REGISTER 9-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 RBPU INTEDG0 bit 7 bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values bit 6 INTEDG0: External Interrupt 0 Edge Select bit 1 = Interrupt on rising edge ...
Page 111
... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2006 Microchip Technology Inc. PIC18F87J10 R/W-0 R/W-0 R/W-0 R/W-0 ...
Page 112
... PIC18F87J10 9.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 9-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
Page 113
... Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1/TMR3 register compare match occurred PWM mode: Unused in this mode. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 U-0 U-0 R/W-0 U-0 — — BCL1IF — Writable bit U = Unimplemented bit, read as ‘ ...
Page 114
... PIC18F87J10 REGISTER 9-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 SSP2IF BCL2IF bit 7 bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software Waiting to transmit/receive bit 6 BCL2IF: Bus Collision Interrupt Flag bit (MSSP2 module bus collision occurred (must be cleared in software) ...
Page 115
... Value at POR © 2006 Microchip Technology Inc. R/W-0 R/W-0 R/W-0 ADIE RC1IE TX1IE SSP1IE W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 R/W-0 R/W-0 R/W-0 CCP1IE TMR2IE TMR1IE bit Bit is unknown DS39663D-page 113 ...
Page 116
... PIC18F87J10 REGISTER 9-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 OSCFIE CMIE bit 7 bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit 1 = Enabled 0 = Disabled bit 5-4 Unimplemented: Read as ‘0’ bit 3 BCL1IE: Bus Collision Interrupt Enable bit (MSSP1 module) ...
Page 117
... CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 R-0 R-0 R/W-0 R/W-0 RC2IE TX2IE TMR4IE CCP5IE W = Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 118
... PIC18F87J10 9.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
Page 119
... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 U-0 U-0 R/W-1 U-0 — — BCL1IP — Writable bit U = Unimplemented bit, read as ‘0’ ...
Page 120
... PIC18F87J10 REGISTER 9-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 SSP2IP BCL2IP bit 7 bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 BCL2IP: Bus Collision Interrupt Priority bit (MSSP2 module High priority 0 = Low priority bit 5 RC2IP: EUSART2 Receive Interrupt Priority bit ...
Page 121
... R = Readable bit -n = Value at POR © 2006 Microchip Technology Inc. U-0 U-0 R/W-1 R-1 — — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 R-1 R/W-0 R/W-0 PD POR BOR bit Bit is unknown DS39663D-page 119 ...
Page 122
... PIC18F87J10 9.6 INTn Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
Page 123
... PORTB PORTC Note 1: These ports are not available on 64-pin devices. Input Buffer and Preliminary PIC18F87J10 input levels. DD OUTPUT DRIVE LEVELS Drive Description Minimum Intended for indication. Medium Sufficient drive levels for external memory interfacing as well as indication. High Suitable for direct LED drive levels ...
Page 124
... PIC18F87J10 10.1.2 INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, pins that also have analog input functions of any kind can only tolerate voltages ...
Page 125
... A/D input channel 4. Default configuration on POR. Bit 5 Bit 4 Bit 3 Bit 2 RA5 RA4 RA3 RA2 LATA5 LATA4 LATA3 LATA2 TRISA5 TRISA4 TRISA3 TRISA2 VCFG1 VCFG0 PCFG3 PCFG2 Preliminary PIC18F87J10 Description Reset Bit 1 Bit 0 Values on page RA1 RA0 52 LATA1 LATA0 52 TRISA1 TRISA0 52 PCFG1 PCFG0 50 DS39663D-page 123 ...
Page 126
... PIC18F87J10 10.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
Page 127
... LATB<7> data output. I TTL PORTB<7> data input; weak pull-up when RBPU bit is cleared. I TTL Interrupt-on-pin change. O DIG Serial execution data output for ICSP and ICD operation Serial execution data input for ICSP and ICD operation. Preliminary PIC18F87J10 Description (2) (2) (2) DS39663D-page 125 ...
Page 128
... PIC18F87J10 TABLE 10-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB7 LATB6 TRISB TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. ...
Page 129
... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2006 Microchip Technology Inc. PIC18F87J10 Note: These pins are configured as digital inputs on any device Reset. The contents of the TRISC register are affected by peripheral overrides ...
Page 130
... PIC18F87J10 TABLE 10-7: PORTC FUNCTIONS TRIS Pin Name Function I/O Setting RC0/T1OSO/ RC0 O 0 T13CKI I 1 T1OSO O x T13CKI I 1 RC1/T1OSI/ RC1 O 0 ECCP2/P2A I 1 T1OSI I x (1) ECCP2 (1) P2A O 0 RC2/ECCP1/ RC2 O 0 P1A I 1 ECCP1 P1A O 0 RC3/SCK1/ RC3 O 0 SCL1 ...
Page 131
... LATC7 LATBC6 TRISC TRISC7 TRISC6 © 2006 Microchip Technology Inc. Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 TRISC2 Preliminary PIC18F87J10 Reset Bit 1 Bit 0 Values on page RC1 RC0 52 LATC1 LATC0 52 TRISC1 TRISC0 52 DS39663D-page 129 ...
Page 132
... PIC18F87J10 10.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
Page 133
... PSP write data input SPI data input (MSSP2 module DIG I C™ data output (MSSP2 module); takes priority over port data data input (MSSP2 module); input type depends on module setting. Preliminary PIC18F87J10 Description (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) (1) DS39663D-page 131 ...
Page 134
... PIC18F87J10 TABLE 10-9: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RD6/AD6/ RD6 0 PSP6/SCK2/ 1 SCL2 (2) AD6 x x PSP6 x x SCK2 0 1 SCL2 0 1 RD7/AD7/ RD7 0 PSP7/SS2 1 (2) AD7 x x PSP7 x x SS2 x Legend: PWR = Power Supply Output Input, ANA = Analog Signal, DIG = Digital Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’ ...
Page 135
... The pull-ups are disabled on any device Reset. © 2006 Microchip Technology Inc. PIC18F87J10 PORTE is also multiplexed with Enhanced PWM outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For all devices, their default assignments are on PORTE< ...
Page 136
... PIC18F87J10 TABLE 10-11: PORTE FUNCTIONS TRIS Pin Name Function Setting RE0/AD8/RD/ RE0 0 P2D 1 (3) AD8 P2D 0 RE1/AD9/WR/ RE1 0 P2C 1 (3) AD9 P2C 0 RE2/AD10/CS/ RE2 0 P2B 1 (3) AD10 P2B 0 RE3/AD11/ RE3 0 P3C 1 (3) AD11 x x (1) P3C 0 RE4/AD12/ RE4 0 P3B 1 (3) AD12 x x (1) ...
Page 137
... Bit 5 Bit 4 Bit 3 Bit 2 RE5 RE4 RE3 RE2 LATE5 LATE4 LATE3 LATE2 TRISE5 TRISE4 TRISE3 TRISE2 (1) RJPU RG4 RG3 RG2 Preliminary PIC18F87J10 Description (2) (2) (2) (2) Reset Bit 1 Bit 0 Values on page RE1 RE0 52 LATE1 LATE0 52 TRISE1 TRISE0 52 RG1 RG0 52 DS39663D-page 135 ...
Page 138
... PIC18F87J10 10.7 PORTF, LATF and TRISF Registers PORTF is a 7-bit wide, bidirectional port. The corre- sponding data direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i ...
Page 139
... RF3 RF2 LATF5 LATF4 LATF3 LATF2 TRISF5 TRISF4 TRISF3 TRISF2 VCFG1 VCFG0 PCFG3 PCFG2 C2INV C1INV CIS CM2 CVRR CVRSS CVR3 CVR2 Preliminary PIC18F87J10 Description Reset Bit 1 Bit 0 Values on page RF1 — 52 LATF1 — 52 TRISF1 — 52 PCFG1 PCFG0 50 CM1 CM0 51 CVR1 ...
Page 140
... PIC18F87J10 10.8 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corre- sponding data direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i ...
Page 141
... PSP data. May be configured for tri-state during Enhanced PWM shutdown events. Bit 5 Bit 4 Bit 3 Bit 2 (1) RJPU RG4 RG3 RG2 — LATG4 LATG3 LATG2 — TRISG4 TRISG3 TRISG2 Preliminary PIC18F87J10 Description Reset Bit 1 Bit 0 Values on page RG1 RG0 52 LATG1 LATG0 52 TRISG1 TRISG0 52 DS39663D-page 139 ...
Page 142
... PIC18F87J10 10.9 PORTH, LATH and TRISH Registers Note: PORTH is available only on 80-pin devices. PORTH is an 8-bit wide, bidirectional I/O port. The cor- responding data direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 143
... May be configured for tri-state during Enhanced PWM shutdown events. Bit 5 Bit 4 Bit 3 Bit 2 RH5 RH4 RH3 RH2 LATH5 LATH4 LATH3 LATH2 TRISH5 TRISH4 TRISH3 TRISH2 Preliminary PIC18F87J10 Description Reset Bit 1 Bit 0 Values on page RH1 RH0 52 LATH1 LATH0 52 TRISH1 TRISH0 52 DS39663D-page 141 ...
Page 144
... PIC18F87J10 10.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin devices. PORTJ is an 8-bit wide, bidirectional port. The corre- sponding data direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
Page 145
... I/O. Bit 5 Bit 4 Bit 3 Bit 2 RJ5 RJ4 RJ3 RJ2 LATJ5 LATJ4 LATJ3 LATJ2 TRISJ4 TRISJ3 TRISJ2 RJPU RG4 RG3 RG2 Preliminary PIC18F87J10 Description Reset Bit 1 Bit 0 Values on page RJ1 RJ0 52 LATJ1 LATJ0 52 TRISJ1 TRISJ0 52 RG1 RG0 52 DS39663D-page 143 ...
Page 146
... PIC18F87J10 10.11 Parallel Slave Port PORTD can also function as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit PSPMODE (PSPCON<4>) is set asynchronously readable and writable by the external world through RD control input pin (RE0/RD) and WR control input pin (RE1/WR). Note: For 80-pin devices, the Parallel Slave Port is available only in Microcontroller mode ...
Page 147
... PSPIF © 2006 Microchip Technology Inc. R-0 R/W-0 R/W-0 U-0 IBOV PSPMODE — Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 U-0 U-0 U-0 — — — bit Bit is unknown DS39663D-page 145 ...
Page 148
... PIC18F87J10 FIGURE 10-4: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 10-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD7 LATD6 TRISD TRISD7 TRISD6 PORTE RE7 RE6 LATE LATE7 LATE6 TRISE TRISE7 TRISE6 ...
Page 149
... Prescale value Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 The T0CON register (Register 11-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 11-1. Figure 11-2 shows a simplified block diagram of the Timer0 module in 16-bit mode ...
Page 150
... PIC18F87J10 11.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 11.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... Since Timer0 is shut down in Sleep mode, the TMR0 interrupt cannot awaken the processor from Sleep. Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF T0CS T0SE PSA T0PS2 TRISA5 TRISA4 TRISA3 TRISA2 Preliminary PIC18F87J10 Reset Bit 1 Bit 0 Values on page 50 50 INT0IF RBIF 49 T0PS1 T0PS0 50 TRISA1 TRISA0 52 DS39663D-page 149 ...
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... PIC18F87J10 NOTES: DS39663D-page 150 Preliminary © 2006 Microchip Technology Inc. ...
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... TMR1ON (T1CON<0>). R/W-0 R/W-0 R/W-0 T1CKPS1 T1CKPS0 T1OSCEN /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 R/W-0 R/W-0 R/W-0 T1SYNC TMR1CS TMR1ON bit Bit is unknown DS39663D-page 151 ...
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... PIC18F87J10 12.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 12-1: TIMER1 BLOCK DIAGRAM ...
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... XTAL 32.768 kHz T1OSO Note: See the Notes with Table 12-1 for additional information about capacitor selection. © 2006 Microchip Technology Inc. PIC18F87J10 TABLE 12-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. Type LP 32 kHz Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F87J10 12.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 12-3, should be located as close as possible to the microcontroller. ...
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... Reset hours ; Done Bit 5 Bit 4 Bit 3 Bit 2 TMR0IE INT0IE RBIE TMR0IF RC1IF TX1IF SSP1IF CCP1IF RC1IE TX1IE SSP1IE CCP1IE RC1IP TX1IP SSP1IP CCP1IP Preliminary PIC18F87J10 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 TMR2IP TMR1IP TMR1CS TMR1ON 50 DS39663D-page 155 ...
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... PIC18F87J10 NOTES: DS39663D-page 156 Preliminary © 2006 Microchip Technology Inc. ...
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... T2CKPS1:T2CKPS0: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 13.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
Page 160
... PIC18F87J10 13.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
Page 161
... Resources” for more information. R/W-0 R/W-0 R/W-0 T3CKPS1 T3CKPS0 T3CCP1 /4) OSC W = Writable bit U = Unimplemented bit, read as ‘0’ ‘1’ = Bit is set ‘0’ = Bit is cleared Preliminary PIC18F87J10 “CCP Modules and Timer R/W-0 R/W-0 R/W-0 T3SYNC TMR3CS TMR3ON bit Bit is unknown DS39663D-page 159 ...
Page 162
... PIC18F87J10 14.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 14-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS1:T3CKPS0 T3SYNC TMR3ON CCPx Special Event Trigger CCPx Select from T3CON<6,3> Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. ...
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... Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — — BCL1IF — — — BCL1IE — — — BCL1IP — T3SYNC Preliminary PIC18F87J10 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 TMR3IF CCP2IF 51 TMR3IE CCP2IE 51 TMR3IP CCP2IP TMR1CS TMR1ON 50 ...
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... PIC18F87J10 NOTES: DS39663D-page 162 Preliminary © 2006 Microchip Technology Inc. ...
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... Prescaler Prescaler is 16 Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 15.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...
Page 166
... PIC18F87J10 15.2 Timer4 Interrupt The Timer4 module has an 8-bit period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 15-1: ...
Page 167
... CAPTURE/COMPARE/PWM (CCP) MODULES Members of the PIC18F87J10 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ...
Page 168
... PIC18F87J10 16.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. 16.1.1 ...
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... T3CCP2 4 Set CCP5IF 4 4 T3CCP1 T3CCP2 and Edge Detect T3CCP2 T3CCP1 Preliminary PIC18F87J10 CHANGING BETWEEN CAPTURE PRESCALERS (CCP5 SHOWN) ; Turn CCP module off ; Load WREG with the ; new prescaler mode ; value and CCP ON ; Load CCP5CON with ; this value TMR3H TMR3L TMR3 ...
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... PIC18F87J10 16.3 Compare Mode In Compare mode, the 16-bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remains unchanged (that is, reflects the state of ...
Page 171
... RC2IP TX2IP TMR4IP CCP5IP — TRISG4 TRISG3 TRISG2 T1CKPS1 T1CKPS0 T1OSCEN T1SYNC T3SYNC DC4B1 DC4B0 CCP4M3 CCP4M2 CCP4M1 CCP4M0 DC5B1 DC5B0 CCP5M3 CCP5M2 CCP5M1 CCP5M0 Preliminary PIC18F87J10 Reset Bit 1 Bit 0 Values on page INT0IF RBIF 49 PD POR BOR 50 TMR2IF TMR1IF 51 TMR2IE TMR1IE 51 ...
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... PIC18F87J10 16.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. Note: ...
Page 173
... Set the TMR2 (TMR4) prescale value, then enable Timer2 (Timer4) by writing to T2CON (T4CON). ) OSC 5. Configure the CCPx module for PWM operation. bits 9.77 kHz 39.06 kHz FFh FFh Preliminary PIC18F87J10 156.25 kHz 312.50 kHz 416.67 kHz 3Fh 1Fh 17h 8 7 6.58 DS39663D-page 171 ...
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... PIC18F87J10 TABLE 16-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN — PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR3 SSP2IF BCL2IF PIE3 SSP2IE BCL2IE IPR3 SSP2IP BCL2IP TRISG — — TMR2 ...
Page 175
... ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE In the PIC18F87J10 family of devices, three of the CCP modules are implemented as standard CCP modules with Enhanced PWM capabilities. These include the provision for output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The Enhanced features are discussed in detail in Section 17.4 “ ...
Page 176
... PIC18F87J10 17.1 ECCP Outputs and Configuration Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCP pin assignments are constant, while others change based on device configuration ...
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... RE7 P2A RE7 P2A RE7 RC1/T1OS1 ECCP2 RC1/T1OS1 P2A RC1/T1OS1 P2A RC1/T1OS1 RE7/AD15 P2A RC1/T1OS1 RE7/AD15 P2A RC1/T1OS1 RE7/AD15 Preliminary PIC18F87J10 RG4 RH7 RH6 RG4/CCP5 N/A N/A RG4/CCP5 N/A N/A P1D N/A N/A RG4/CCP5 RH7/AN15 RH6/AN14 RG4/CCP5 P1B RH6/AN14 P1D P1B ...
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... PIC18F87J10 TABLE 17-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON ECCP Mode Configuration Compatible CCP ECCP3 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP ECCP3 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx ...
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... PWM output. P1M1<1:0> CCP1M<3:0> ECCP1/P1A TRISx<x> P1B TRISx<x> Output R Q Controller P1C TRISx<x> S P1D TRISx<x> ECCP1DEL Preliminary PIC18F87J10 • OSC (TMR2 Prescale Value) ECCP1/P1A P1B P1C P1D DS39663D-page 177 ...
Page 180
... PIC18F87J10 17.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is ...
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... OSC • Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: Dead-band delay is programmed using the ECCP1DEL register (Section 17.4.6 “Programmable Dead-Band Delay”). © 2006 Microchip Technology Inc. PIC18F87J10 0 Duty Cycle Period (1) (1) Delay Delay 0 Duty ...
Page 182
... DS39663D-page 180 FIGURE 17-4: Duty Cycle (2) P1A td (2) P1B ( Dead Band Delay Note 1: At this time, the TMR2 register is equal to the PR2 register. 2: Output signals are shown as active-high. V+ PIC18F87J10 FET Driver P1A FET Driver P1B V- V+ FET Driver Load FET Driver ...
Page 183
... P1A, P1B, P1C and P1D outputs are multiplexed with the port pins as described in Table 17-1, Table 17-2 and Table 17-3. The corresponding TRIS bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs. Period Duty Cycle Period Duty Cycle Preliminary PIC18F87J10 (1) (1) DS39663D-page 181 ...
Page 184
... PIC18F87J10 FIGURE 17-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F87J10 P1A P1B P1C P1D 17.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
Page 185
... QC and its driver the turn-off delay of power switch QD and its driver. OFF © 2006 Microchip Technology Inc. (1) Period DC , depending on the Timer2 prescaler value. The modulated P1B and P1D signals OSC Forward Period t1 DC Preliminary PIC18F87J10 Period (Note 2) Reverse Period DC ( (3) t OFF (2, – t OFF ...
Page 186
... PIC18F87J10 17.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on ...
Page 187
... PWM pins are configured as outputs. Changing the polarity configura- tion while the PWM pins are configured as outputs is not recommended since it may result in damage to the application circuits. Preliminary PIC18F87J10 R/W-0 R/W-0 R/W-0 bit Bit is unknown DS39663D-page 185 ...
Page 188
... PIC18F87J10 The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP1 module may cause damage to the applica- tion circuit. The ECCP1 module must be enabled in the ...
Page 189
... EFFECTS OF A RESET Both Power-on Reset and subsequent Resets will force all ports to Input mode and the ECCP registers to their Reset states. This forces the Enhanced CCP module to reset to a set the state compatible with the standard CCP module. Preliminary PIC18F87J10 DS39663D-page 187 ...
Page 190
... PIC18F87J10 TABLE 17-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN — PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP PIR3 SSP2IF BCL2IF ...
Page 191
... Master mode • Multi-Master mode • Slave mode (with address masking for both 10-bit and 7-bit addressing) All members of the PIC18F87J10 family have two MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. Note: Throughout this section, generic refer- ...
Page 192
... PIC18F87J10 18.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPxCON1) • MSSP Status Register (SSPxSTAT) • Serial Receive/Transmit Buffer Register (SSPxBUF) • MSSP Shift Register (SSPxSR) – Not directly accessible SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation ...
Page 193
... SPI Master mode, clock = F 0000 = SPI Master mode, clock = F Note: Bit combinations not specifically listed here are either reserved or implemented mode only. Legend Readable bit -n = Value at POR © 2006 Microchip Technology Inc. PIC18F87J10 R/W-0 R/W-0 R/W-0 R/W-0 SSPEN CKP SSPM3 SSPM2 /64 OSC ...
Page 194
... PIC18F87J10 18.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCKx is the clock output) • Slave mode (SCKx is the clock input) • ...
Page 195
... Master sends data – Slave sends data • Master sends dummy data – Slave sends data SPI Slave SSPM3:SSPM0 = 010xb SDOx SDIx Serial Input Buffer SDIx SDOx MSb Serial Clock SCKx SCKx Preliminary PIC18F87J10 (SSPxBUF) Shift Register (SSPxSR) LSb PROCESSOR 2 DS39663D-page 193 ...
Page 196
... PIC18F87J10 18.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 1, Figure 18- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be dis- abled (programmed as an input) ...
Page 197
... SDOx pin can be configured as an input. This disables transmissions from the SDOx. The SDIx can always be left as an input (SDI function) since it cannot create a bus conflict. bit 6 bit 7 bit 7 Preliminary PIC18F87J10 SPI is in Slave mode SSx pin control enabled the SPI ...
Page 198
... PIC18F87J10 FIGURE 18-5: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = SSx Optional SCKx (CKP = 0 CKE = 0) SCKx (CKP = 1 CKE = 0) Write to SSPxBUF SDOx bit 7 SDIx (SMP = 0) bit 7 Input Sample (SMP = 0) SSPxIF Interrupt Flag SSPxSR to SSPxBUF FIGURE 18-6: SPI MODE WAVEFORM (SLAVE MODE WITH CKE = 1) ...
Page 199
... EFFECTS OF A RESET A Reset disables the MSSP module and terminates the current transfer. © 2006 Microchip Technology Inc. PIC18F87J10 18.3.10 BUS MODE COMPATIBILITY Table 18-1 shows the compatibility between the standard SPI modes and the states of the CKP and CKE control bits. ...
Page 200
... PIC18F87J10 TABLE 18-2: REGISTERS ASSOCIATED WITH SPI OPERATION Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL TMR0IE PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR3 SSP2IF BCL2IF PIE3 SSP2IE BCL2IE IPR3 SSP2IP BCL2IP TRISC TRISC7 TRISC6 TRISD TRISD7 TRISD6 TRISF TRISF7 ...