PIC18F87J10-I/PT Microchip Technology, PIC18F87J10-I/PT Datasheet
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PIC18F87J10-I/PT Summary of contents
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... Microchip Technology Inc. PIC18F87J10 Family 64/80-Pin, High-Performance 1-Mbit Flash Microcontrollers with nanoWatt Technology Data Sheet DS39663F ...
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... REAL ICE, rfLAB, Select Mode, Total Endurance, TSHARC, UniWinDriver, WiperLock and ZENA are trademarks of Microchip Technology Incorporated in the U.S.A. and other countries. SQTP is a service mark of Microchip Technology Incorporated in the U.S.A. All other trademarks mentioned herein are property of their respective companies. ...
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... Secondary Oscillator using Timer1 @ 32 kHz • Two-Speed Oscillator Start-up • Fail-Safe Clock Monitor: - Allows for safe shutdown if peripheral clock stops © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Peripheral Highlights: • High-Current Sink/Source 25 mA/25 mA (PORTB and PORTC) • Four Programmable External Interrupts • ...
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... PIC18F87J10 FAMILY Program Memory SRAM Data Device Flash # Single-Word (bytes) Instructions PIC18F65J10 32K 16384 PIC18F65J15 48K 24576 PIC18F66J10 64K 32768 PIC18F66J15 96K 49152 PIC18F67J10 128K 65536 PIC18F85J10 32K 16384 PIC18F85J15 48K 24576 PIC18F86J10 64K 32768 PIC18F86J15 96K 49152 PIC18F87J10 128K 65536 ...
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... RH7/AN15/P1B 19 (2) RH6/AN14/P1C 20 Note 1: The ECCP2/P2A pin placement depends on the setting of the CCP2MX Configuration bit and the program memory mode. 2: P1B, P1C, P3B and P3C pin placement depends on the setting of the ECCPMX Configuration bit. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY ...
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... PIC18F87J10 FAMILY Table of Contents 1.0 Device Overview .......................................................................................................................................................................... 5 2.0 Guidelines for Getting Started with PIC18FJ Microcontrollers ................................................................................................... 27 3.0 Oscillator Configurations ............................................................................................................................................................ 31 4.0 Power-Managed Modes ............................................................................................................................................................. 39 5.0 Reset .......................................................................................................................................................................................... 47 6.0 Memory Organization ................................................................................................................................................................. 59 7.0 Flash Program Memory .............................................................................................................................................................. 85 8.0 External Memory Bus ................................................................................................................................................................. 95 9 Hardware Multiplier.......................................................................................................................................................... 107 10.0 Interrupts .................................................................................................................................................................................. 109 11 ...
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... OSCILLATOR OPTIONS AND FEATURES All of the devices in the PIC18F87J10 family offer five different oscillator options, allowing users a range of choices in developing application hardware. These include: • Two Crystal modes, using crystals or ceramic resonators. ...
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... Section 27.0 “Electrical Characteristics” for time-out periods. DS39663F-page 6 1.3 Details on Individual Family Members Devices in the PIC18F87J10 family are available in 64-pin and 80-pin packages. Block diagrams for the two groups are shown in Figure 1-1 and Figure 1-2. The devices are differentiated from each other in four ways: 1. ...
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... TABLE 1-1: DEVICE FEATURES FOR THE PIC18F87J10 FAMILY (64-PIN DEVICES) Features PIC18F65J10 Operating Frequency DC – 40 MHz Program Memory (Bytes) Program Memory (Instructions) Data Memory (Bytes) Interrupt Sources I/O Ports Timers Capture/Compare/PWM Modules Enhanced Capture/ Compare/PWM Modules Serial Communications Parallel Communications (PSP) ...
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... PIC18F87J10 FAMILY FIGURE 1-1: PIC18F6XJ10/6XJ15 (64-PIN) BLOCK DIAGRAM Table Pointer<21> inc/dec logic 21 20 Address Latch Program Memory (96 Kbytes) Data Latch 8 Table Latch ROM Latch Instruction Bus <16> Instruction Decode and Power-up Timing OSC2/CLKO Generation OSC1/CLKI Oscillator Start-up Timer INTRC Oscillator Power-on ...
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... ECCP1 ECCP2 ECCP3 Note 1: See Table 1-4 for I/O port pin descriptions. 2: BOR functionality is provided when the on-board voltage regulator is enabled. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Data Latch 8 8 Data Memory (2.0, 3.9 Kbytes) PCLATH PCLATU Address Latch ...
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... PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS Pin Number Pin Name TQFP MCLR 7 OSC1/CLKI 39 OSC1 CLKI OSC2/CLKO 40 OSC2 CLKO RA0/AN0 24 RA0 AN0 RA1/AN1 23 RA1 AN1 RA2/AN2 REF RA2 AN2 V - REF RA3/AN3 REF RA3 AN3 V + REF RA4/T0CKI 28 RA4 T0CKI RA5/AN4 27 RA5 ...
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... C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTB is a bidirectional I/O port. PORTB can be software programmed for internal weak pull-ups on all inputs ...
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... PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RC0/T1OSO/T13CKI 30 RC0 T1OSO T13CKI RC1/T1OSI/ECCP2/P2A 29 RC1 T1OSI (1) ECCP2 (1) P2A RC2/ECCP1/P1A 33 RC2 ECCP1 P1A RC3/SCK1/SCL1 34 RC3 SCK1 SCL1 RC4/SDI1/SDA1 35 RC4 SDI1 SDA1 RC5/SDO1 36 RC5 SDO1 RC6/TX1/CK1 31 RC6 TX1 ...
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... C/SMB = I C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTD is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RE0/RD/P2D 2 RE0 RD P2D RE1/WR/P2C 1 RE1 WR P2C RE2/CS/P2B 64 RE2 CS P2B RE3/P3C 63 RE3 P3C RE4/P3B 62 RE4 P3B RE5/P1C 61 RE5 P1C RE6/P1B 60 RE6 P1B RE7/ECCP2/P2A 59 RE7 (2) ECCP2 (2) P2A Legend: TTL ...
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... C/SMB = I C™/SMBus input buffer Note 1: Default assignment for ECCP2/P2A when Configuration bit, CCP2MX, is set. 2: Alternate assignment for ECCP2/P2A when Configuration bit, CCP2MX, is cleared. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTF is a bidirectional I/O port. I/O ST Digital I/O ...
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... PIC18F87J10 FAMILY TABLE 1-3: PIC18F6XJ10/6XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RG0/ECCP3/P3A 3 RG0 ECCP3 P3A RG1/TX2/CK2 4 RG1 TX2 CK2 RG2/RX2/DT2 5 RG2 RX2 DT2 RG3/CCP4/P3D 6 RG3 CCP4 P3D RG4/CCP5/P1D 8 RG4 CCP5 P1D V 9, 25, 41 26, 38 ENVREG DDCORE CAP V DDCORE ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type I ST Master Clear (Reset) input. This pin is an active-low Reset to the device ...
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... PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RB0/INT0/FLT0 58 RB0 INT0 FLT0 RB1/INT1 57 RB1 INT1 RB2/INT2 56 RB2 INT2 RB3/INT3/ECCP2/P2A 55 RB3 INT3 (1) ECCP2 (1) P2A RB4/KBI0 54 RB4 KBI0 RB5/KBI1 53 RB5 KBI1 RB6/KBI2/PGC 52 RB6 KBI2 PGC RB7/KBI3/PGD 47 RB7 ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTC is a bidirectional I/O port. ...
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... PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RD0/AD0/PSP0 72 RD0 AD0 PSP0 RD1/AD1/PSP1 69 RD1 AD1 PSP1 RD2/AD2/PSP2 68 RD2 AD2 PSP2 RD3/AD3/PSP3 67 RD3 AD3 PSP3 RD4/AD4/PSP4/SDO2 66 RD4 AD4 PSP4 SDO2 RD5/AD5/PSP5/ 65 SDI2/SDA2 RD5 AD5 PSP5 SDI2 ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTE is a bidirectional I/O port. ...
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... PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RF1/AN6/C2OUT 23 RF1 AN6 C2OUT RF2/AN7/C1OUT 18 RF2 AN7 C1OUT RF3/AN8 17 RF3 AN8 RF4/AN9 16 RF4 AN9 RF5/AN10/CV 15 REF RF5 AN10 CV REF RF6/AN11 14 RF6 AN11 RF7/SS1 13 RF7 SS1 Legend: TTL ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTG is a bidirectional I/O port. ...
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... PIC18F87J10 FAMILY TABLE 1-4: PIC18F8XJ10/8XJ15 PINOUT I/O DESCRIPTIONS (CONTINUED) Pin Number Pin Name TQFP RH0/A16 79 RH0 A16 RH1/A17 80 RH1 A17 RH2/A18 1 RH2 A18 RH3/A19 2 RH3 A19 RH4/AN12/P3C 22 RH4 AN12 (5) P3C RH5/AN13/P3B 21 RH5 AN13 (5) P3B RH6/AN14/P1C 20 RH6 AN14 (5) P1C RH7/AN15/P1B 19 RH7 AN15 ...
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... Default assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is set). 4: Alternate assignment for ECCP2/P2A when CCP2MX is cleared (Microcontroller mode). 5: Alternate assignments for P1B/P1C/P3B/P3C (ECCPMX Configuration bit is cleared). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Pin Buffer Type Type PORTJ is a bidirectional I/O port. ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 26 © 2009 Microchip Technology Inc. ...
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... GUIDELINES FOR GETTING STARTED WITH PIC18FJ MICROCONTROLLERS 2.1 Basic Connection Requirements Getting started with the PIC18F87J10 family of 8-bit microcontrollers requires attention to a minimal set of device pin connections before proceeding with development. The following pins must always be connected: • All V and V ...
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... PIC18F87J10 FAMILY 2.2 Power Supply Pins 2.2.1 DECOUPLING CAPACITORS The use of decoupling capacitors on every pair of power supply pins, such required. SS Consider the following criteria when using decoupling capacitors: • Value and type of capacitor: A 0.1 μF (100 nF), 10-20V capacitor is recommended. The capacitor should be a low-ESR device with a resonance frequency in the range of 200 MHz and higher ...
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... Frequency (MHz) Note: Data for Murata GRM21BF50J106ZE01 shown. Measurements at 25° bias. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 2.5 ICSP Pins The PGC and PGD pins are used for In-Circuit Serial Programming (ICSP) and debugging purposes recommended to keep the trace length between the ...
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... PIC18F87J10 FAMILY 2.6 External Oscillator Pins Many microcontrollers have options for at least two oscillators: a high-frequency primary oscillator and a low-frequency secondary oscillator Section 3.0 “Oscillator Configurations” for details). The oscillator circuit should be placed on the same side of the board as the device. Place the oscillator circuit close to the respective oscillator pins with no more than 0 ...
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... OSCILLATOR CONFIGURATIONS 3.1 Oscillator Types The PIC18F87J10 family of devices can be operated in five different oscillator modes High-Speed Crystal/Resonator 2. HSPLL High-Speed Crystal/Resonator with Software PLL Control 3. EC External Clock with F OSC 4. ECPLL External Clock with Software PLL Control 5. INTRC Internal 31 kHz Oscillator Four of these are selected by the user by programming the FOSC< ...
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... PIC18F87J10 FAMILY TABLE 3-2: CAPACITOR SELECTION FOR CRYSTAL OSCILLATOR Typical Capacitor Values Crystal Tested: Osc Type Freq MHz MHz MHz 15 pF Capacitor values are for design guidance only. These capacitors were tested with the crystals listed below for basic start-up and operation. These values are not optimized ...
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... Unimplemented: Read as ‘0’ Note 1: Available only for ECPLL and HSPLL oscillator configurations; otherwise, this bit is unavailable and read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY FIGURE 3-4: PLL BLOCK DIAGRAM HSPLL or ECPLL (CONFIG2L) PLL Enable (OSCTUNE) OSC2 ...
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... The INTRC source is also used as the clock source for several special features, such as the WDT and Fail-Safe Clock Monitor. The clock sources for the PIC18F87J10 family devices are shown in Figure 3-5. See Section 24.0 “Special Features of the CPU” for Configuration register details. ...
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... FOSC2. 3.6.2 OSCILLATOR TRANSITIONS PIC18F87J10 family devices contain circuitry to prevent clock “glitches” when switching between clock sources. A short pause in the device clock occurs during the clock switch. The length of this pause is the sum of two cycles of the old clock source and three to four cycles of the new clock source ...
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... PIC18F87J10 FAMILY REGISTER 3-2: OSCCON: OSCILLATOR CONTROL REGISTER R/W-0 U-0 U-0 IDLEN — — bit 7 Legend Value determined by configuration R = Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IDLEN: Idle Enable bit 1 = Device enters Idle mode on SLEEP instruction 0 = Device enters Sleep mode on SLEEP instruction bit 6-4 Unimplemented: Read as ‘ ...
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... Note: See Table 5-2 in Section 5.0 “Reset” for time-outs due to Sleep and MCLR Reset. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Timer1 oscillator may be operating to support a Real-Time Clock. Other features may be operating that do not require a device clock source (i.e., MSSP slave, PSP, INTx pins and others) ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 38 © 2009 Microchip Technology Inc. ...
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... POWER-MANAGED MODES The PIC18F87J10 family devices provide the ability to manage power consumption by simply managing clock- ing to the CPU and the peripherals. In general, a lower clock frequency and a reduction in the number of circuits being clocked constitutes lower consumed power. For the sake of managing power in an application, there are three primary modes of operation: • ...
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... PIC18F87J10 FAMILY 4.1.3 CLOCK TRANSITIONS AND STATUS INDICATORS The length of the transition between clock sources is the sum of two cycles of the old clock source and three to four cycles of the new clock source. This formula assumes that the new clock source is stable. Two bits indicate the current clock source and its ...
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... These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY On transitions from SEC_RUN mode to PRI_RUN, the peripherals and CPU continue to be clocked from the Timer1 oscillator while the primary clock is started. When the primary clock becomes ready, a clock switch back to the primary clock occurs (see Figure 4-2) ...
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... PIC18F87J10 FAMILY 4.2.3 RC_RUN MODE In RC_RUN mode, the CPU and peripherals are clocked from the internal oscillator; the primary clock is shut down. This mode provides the best power conser- vation of all the Run modes while still executing code. It works well for user applications which are not highly timing sensitive or do not require high-speed clocks at all times ...
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... These intervals are not shown to scale. OST OSC PLL © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 4.4 Idle Modes The Idle modes allow the controller’s CPU to be selectively shut down while the peripherals continue to operate. Selecting a particular Idle mode allows users to further manage power consumption. If the IDLEN bit is set to a ‘ ...
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... PIC18F87J10 FAMILY 4.4.1 PRI_IDLE MODE This mode is unique among the three low-power Idle modes, in that it does not disable the primary device clock. For timing-sensitive applications, this allows for the fastest resumption of device operation with its more accurate primary clock source, since the clock source does not have to “ ...
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... CPU to prepare for execution. Instruction execution resumes on the first clock cycle following this delay. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 4.5.2 EXIT BY WDT TIME-OUT A WDT time-out will cause different actions depending on which power-managed mode the device is in when the time-out occurs ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 46 © 2009 Microchip Technology Inc. ...
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... RESET The PIC18F87J10 family of devices differentiate between various kinds of Reset: a) Power-on Reset (POR) b) MCLR Reset during normal operation c) MCLR Reset during power-managed modes d) Watchdog Timer (WDT) Reset (during execution) e) Brown-out Reset (BOR) f) RESET Instruction g) Stack Full Reset h) Stack Underflow Reset ...
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... PIC18F87J10 FAMILY REGISTER 5-1: RCON: RESET CONTROL REGISTER R/W-0 U-0 U-0 IPEN — — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 IPEN: Interrupt Priority Enable bit 1 = Enable priority levels on interrupts 0 = Disable priority levels on interrupts (PIC16CXXX Compatibility mode) bit 6-5 Unimplemented: Read as ‘ ...
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... To capture multiple events, the user manually resets the bit to ‘1’ in software following any POR. 5.4 Brown-out Reset (BOR) The PIC18F87J10 family of devices incorporate a simple BOR function when the internal regulator is enabled (ENVREG pin is tied Any drop ...
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... Reset process. The PWRT is always enabled. The main function is to ensure that the device voltage is stable before code is executed. The Power-up Timer (PWRT) of the PIC18F87J10 family devices is an 11-bit counter which uses the INTRC source as the clock input. This yields an approximate time interval of 2048 x 32 μ ...
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... TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET FIGURE 5-6: SLOW RISE TIME (MCLR TIED MCLR INTERNAL POR PWRT TIME-OUT INTERNAL RESET © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY T PWRT , V RISE > 3. PWRT ): CASE PWRT DS39663F-page 51 ...
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... PIC18F87J10 FAMILY 5.6 Reset State of Registers Most registers are unaffected by a Reset. Their status is unknown on POR and unchanged by all other Resets. The other registers are forced to a “Reset state” depending on the type of Reset that occurred. Most registers are not affected by a WDT wake-up, since this is viewed as the resumption of normal operation ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction Stack Resets ...
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... PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices INDF2 PIC18F6XJ1X PIC18F8XJ1X POSTINC2 PIC18F6XJ1X PIC18F8XJ1X POSTDEC2 PIC18F6XJ1X PIC18F8XJ1X PREINC2 PIC18F6XJ1X PIC18F8XJ1X PLUSW2 PIC18F6XJ1X PIC18F8XJ1X FSR2H PIC18F6XJ1X PIC18F8XJ1X FSR2L PIC18F6XJ1X PIC18F8XJ1X STATUS PIC18F6XJ1X PIC18F8XJ1X TMR0H PIC18F6XJ1X PIC18F8XJ1X TMR0L ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction Stack Resets ...
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... PIC18F87J10 FAMILY TABLE 5-2: INITIALIZATION CONDITIONS FOR ALL REGISTERS (CONTINUED) Register Applicable Devices TRISJ PIC18F6XJ1X PIC18F8XJ1X TRISH PIC18F6XJ1X PIC18F8XJ1X TRISG PIC18F6XJ1X PIC18F8XJ1X TRISF PIC18F6XJ1X PIC18F8XJ1X TRISE PIC18F6XJ1X PIC18F8XJ1X TRISD PIC18F6XJ1X PIC18F8XJ1X TRISC PIC18F6XJ1X PIC18F8XJ1X TRISB PIC18F6XJ1X PIC18F8XJ1X TRISA PIC18F6XJ1X PIC18F8XJ1X LATJ ...
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... One or more bits in the INTCONx or PIRx registers will be affected (to cause wake-up). 4: See Table 5-1 for Reset value for specific condition. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY MCLR Resets Power-on Reset, WDT Reset Brown-out Reset RESET Instruction Stack Resets ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 58 © 2009 Microchip Technology Inc. ...
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... Accessing a location between the upper boundary of the physically implemented memory and the 2-Mbyte address will return all ‘0’s (a NOP instruction). The entire PIC18F87J10 family offers a range of on-chip Flash program memory sizes, from 32 Kbytes (up to 16,384 single-word instructions) to 128 Kbytes (65,536 ...
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... CONFIG1 CONFIG3, are used; CONFIG4 is reserved. The actual addresses of the Flash Configuration Word for devices in the PIC18F87J10 family are shown in Table 6-1. Their location in the memory map is shown with the other memory vectors in Figure 6-2. Additional details on the device Configuration Words are provided in Section 24.1 “ ...
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... Address shifting disabled – external address bus reflects the PC value bit 2-0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY • The Extended Microcontroller Mode allows access to both internal and external program memories as a single block. The device can access its entire on-chip program memory ...
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... In practical terms, this means addresses in the external memory device below the top of on-chip memory are unavailable. FIGURE 6-3: MEMORY MAPS FOR PIC18F87J10 FAMILY PROGRAM MEMORY MODES (1) Microcontroller Mode Extended Microcontroller Mode On-Chip ...
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... Microchip Technology Inc. PIC18F87J10 FAMILY The stack operates as a 31-word by 21-bit RAM and a 5-bit Stack Pointer, STKPTR. The stack space is not part of either program or data space. The Stack Pointer is readable and writable and the address on the top of the stack is readable and writable through the Top-of-Stack Special Function Registers ...
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... PIC18F87J10 FAMILY 6.1.6.2 Return Stack Pointer (STKPTR) The STKPTR register (Register 6-2) contains the Stack Pointer value, the STKFUL (Stack Full) status bit and the STKUNF (Stack Underflow) status bit. The value of the Stack Pointer can be 0 through 31. The Stack Pointer increments before values are pushed onto the stack and decrements after values are popped off the stack ...
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... SUB1 • RETURN FAST ;RESTORE VALUES SAVED ;IN FAST REGISTER STACK © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 6.1.8 LOOK-UP TABLES IN PROGRAM MEMORY There may be programming situations that require the creation of data structures, or look-up tables, in program memory. For PIC18 devices, look-up tables can be implemented in two ways: • ...
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... PIC18F87J10 FAMILY 6.2 PIC18 Instruction Cycle 6.2.1 CLOCKING SCHEME The microcontroller clock input, whether from an internal or external source, is internally divided by four to generate four non-overlapping quadrature clocks (Q1, Q2, Q3 and Q4). Internally, the program counter is incremented on every Q1; the instruction is fetched from the program memory and latched into the instruc- tion register during Q4 ...
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... ADDWF © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The CALL and GOTO instructions have the absolute program memory address embedded into the instruc- tion. Since instructions are always stored on word boundaries, the data contained in the instruction is a word address. The word address is written to PC< ...
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... PIC18F87J10 FAMILY 6.3 Data Memory Organization Note: The operation of some aspects of data memory are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. The data memory in PIC18 devices is implemented as static RAM ...
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... FFh 00h = 0111 Bank 7 FFh 00h = 1000 Bank 1110 Bank 14 FFh 00h = 1111 Bank 15 FFh © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Data Memory Map 000h Access RAM 05Fh 060h GPR 0FFh 100h GPR 1FFh 200h GPR 2FFh 300h GPR 3FFh ...
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... PIC18F87J10 FAMILY FIGURE 6-8: DATA MEMORY MAP FOR PIC18FX6J15/X7J10 DEVICES BSR<3:0> 00h = 0000 Bank 0 FFh 00h = 0001 Bank 1 FFh 00h = 0010 Bank 2 FFh 00h = 0011 Bank 3 FFh 00h = 0100 Bank 4 FFh 00h = 0101 Bank 5 FFh 00h = 0110 Bank 6 FFh 00h = 0111 ...
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... BSR and the 8-bit address included in the opcode for the data memory address. When ‘a’ is ‘0’, however, the instruction is forced to use the Access Bank address map; the current value of the BSR is ignored entirely. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Data Memory 000h 7 00h Bank 0 ...
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... RAM. SFRs start at the top of data memory (FFFh) and extend downward to occupy more than the top half of Bank 15 (F60h to FFFh). A list of these registers is given in Table 6-3 and Table 6-4. TABLE 6-3: SPECIAL FUNCTION REGISTER MAP FOR PIC18F87J10 FAMILY DEVICES Address Name Address FFFh ...
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... TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) File Name Bit 7 Bit 6 Bit 5 TOSU — — TOSH Top-of-Stack High Byte (TOS<15:8>) TOSL Top-of-Stack Low Byte (TOS<7:0>) STKPTR STKFUL STKUNF PCLATU — — bit 21 PCLATH Holding Register for PC<15:8> PCL PC Low Byte (PC<7:0>) TBLPTRU — ...
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... PIC18F87J10 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TMR0H Timer0 Register High Byte TMR0L Timer0 Register Low Byte T0CON TMR0ON T08BIT T0CS OSCCON IDLEN — — WDTCON — — — RCON IPEN — — ...
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... TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 TXREG1 EUSART1 Transmit Register TXSTA1 CSRC TX9 TXEN RCSTA1 SPEN RX9 SREN EECON2 Program Memory Control Register 2 (not a physical register) EECON1 — — IPR3 SSP2IP BCL2IP RC2IP PIR3 ...
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... PIC18F87J10 FAMILY TABLE 6-4: REGISTER FILE SUMMARY (PIC18F87J10 FAMILY) (CONTINUED) File Name Bit 7 Bit 6 Bit 5 SPBRGH1 EUSART1 Baud Rate Generator Register High Byte BAUDCON1 ABDOVF RCIDL — SPBRGH2 EUSART2 Baud Rate Generator Register High Byte BAUDCON2 ABDOVF RCIDL — ECCP1DEL P1RSEN ...
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... For rotate (RRF, RLF) instructions, this bit is loaded with either the high or low-order bit of the source register. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY register then reads back as ‘000u u1uu’ recom- mended, therefore, that only BCF, BSF, SWAPF, MOVFF ...
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... PIC18F87J10 FAMILY 6.4 Data Addressing Modes Note: The execution of some instructions in the core PIC18 instruction set are changed when the PIC18 extended instruction set is enabled. See Section 6.6 “Data Memory and the Extended Instruction Set” for more information. While the program memory can be addressed in only one way – ...
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... FCCh will be added to that of the W register and stored back in FCCh. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY the SFR space but are not physically implemented. Reading or writing to a particular INDF register actually accesses its corresponding FSR register pair. A read from INDF1, for example, reads the data at the address indicated by FSR1H:FSR1L ...
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... PIC18F87J10 FAMILY 6.4.3.2 FSR Registers and POSTINC, POSTDEC, PREINC and PLUSW In addition to the INDF operand, each FSR register pair also has four additional indirect operands. Like INDF, these are “virtual” registers that cannot be indirectly read or written to. Accessing these registers actually accesses the associated FSR register pair, but also performs a specific action on its stored value ...
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... Indexed Addressing with Literal Offset, or Indexed Literal Offset mode. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY When using the extended instruction set, this addressing mode requires the following: • The use of the Access Bank is forced (‘a’ = 0); ...
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... PIC18F87J10 FAMILY FIGURE 6-11: COMPARING ADDRESSING OPTIONS FOR BIT-ORIENTED AND BYTE-ORIENTED INSTRUCTIONS (EXTENDED INSTRUCTION SET ENABLED) EXAMPLE INSTRUCTION: ADDWF (Opcode: 0010 01da ffff ffff) When and f ≥ 60h: The instruction executes in Direct Forced mode. ‘f’ is interpreted as a location in the Access RAM between 060h and FFFh ...
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... BSR. F60h FFFh © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Remapping of the Access Bank applies only to opera- tions using the Indexed Literal Offset mode. Operations that use the BSR (Access RAM bit is ‘1’) will continue to use Direct Addressing as before. Any Indirect or ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 84 © 2009 Microchip Technology Inc. ...
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... Program Memory (TBLPTR) Note 1: The Table Pointer register points to a byte in program memory. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 7.1 Table Reads and Table Writes In order to read and write program memory, there are two operations that allow the processor to move bytes ...
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... PIC18F87J10 FAMILY FIGURE 7-2: TABLE WRITE OPERATION (1) Table Pointer TBLPTRU TBLPTRH TBLPTRL Program Memory (TBLPTR) Note 1: The Table Pointer actually points to one of 64 holding registers, the address of which is determined by TBLPTRL<5:0>. The process for physically writing data to the program memory array is discussed in Section 7.5 “ ...
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... The WR bit can only be set (not cleared) in software Write cycle is complete bit 0 Unimplemented: Read as ‘0’ © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-x R/W-0 FREE WRERR WREN U = Unimplemented bit, read as ‘ ...
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... PIC18F87J10 FAMILY 7.2.2 TABLE LATCH REGISTER (TABLAT) The Table Latch (TABLAT 8-bit register mapped into the SFR space. The Table Latch register is used to hold 8-bit data during data transfers between program memory and data RAM. 7.2.3 TABLE POINTER REGISTER (TBLPTR) The Table Pointer (TBLPTR) register addresses a byte within the program memory ...
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... MOVF TABLAT, W MOVF WORD_ODD © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY TBLPTR points to a byte address in program space. Executing TBLRD places the byte pointed to into TABLAT. In addition, TBLPTR can be modified automatically for the next table read operation. The internal program memory is typically organized by words ...
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... PIC18F87J10 FAMILY 7.4 Erasing Flash Program Memory The minimum erase block is 512 words or 1024 bytes. Only through the use of an external programmer, or through ICSP control, can larger blocks of program memory be bulk erased. Word erase in the Flash array is not supported. When initiating an erase sequence from the micro- controller itself, a block of 1024 bytes of program memory is erased ...
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... The on-chip timer controls the write time. The write/erase voltages are generated by an on-chip charge pump, rated to operate over the voltage range of the device. Note 1: Unlike previous PIC devices, members of the PIC18F87J10 family do not reset the holding registers after a write occurs. The holding registers must be cleared or overwritten sequence. ...
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... PIC18F87J10 FAMILY EXAMPLE 7-3: WRITING TO FLASH PROGRAM MEMORY MOVLW CODE_ADDR_UPPER MOVWF TBLPTRU MOVLW CODE_ADDR_HIGH MOVWF TBLPTRH MOVLW CODE_ADDR_LOW MOVWF TBLPTRL ERASE_BLOCK BSF EECON1, WREN BSF EECON1, FREE BCF INTCON, GIE MOVLW 55h MOVWF EECON2 MOVLW 0AAh MOVWF EECON2 BSF EECON1, WR BSF ...
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... EECON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used during program memory access. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 7.6 Flash Program Operation During Code Protection See Section 24.6 “Program Verification and Code Protection” for details on code protection of Flash program memory ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 94 © 2009 Microchip Technology Inc. ...
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... For the sake of clarity, only I/O port and external bus assignments are shown here. One or more additional multiplexed features may be available on some pins. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The bus is implemented with 28 pins, multiplexed across four I/O ports. Three ports (PORTD, PORTE ...
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... PIC18F87J10 FAMILY 8.1 External Memory Bus Control The operation of the interface is controlled by the MEMCON register (Register 8-1). This register is available in all program memory operating modes except Microcontroller mode. In this mode, the register is disabled and cannot be written to. The EBDIS bit (MEMCON<7>) controls the operation of the bus and related port functions ...
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... Address and Data Width The PIC18F87J10 family of devices can be indepen- dently configured for different address and data widths on the same memory bus. Both address and data width are set by Configuration bits in the CONFIG3L register. As Configuration bits, this means that these options can only be configured by programming the device and are not controllable in software ...
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... Resets. 8.5 Program Memory Modes and the External Memory Bus The PIC18F87J10 family of devices is capable of operating in one of two program memory modes, using combinations of on-chip and external program memory. The functions of the multiplexed port pins depend on the program memory mode selected, as well as the setting of the EBDIS bit ...
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... BYTE WRITE MODE Figure 8-1 shows an example of 16-Bit Byte Write mode for PIC18F87J10 family devices. This mode is used for two separate 8-bit memories connected for 16-bit operation. This generally includes basic EPROM and Flash devices. It allows table writes to byte-wide external memories ...
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... PIC18F87J10 FAMILY 8.6.2 16-BIT WORD WRITE MODE Figure 8-2 shows an example of 16-Bit Word Write mode for PIC18F65J10 devices. This mode is used for word-wide memories which include some of the EPROM and Flash type memories. This mode allows opcode fetches and table reads from all forms of 16-bit memory and table writes to any type of word-wide external memories ...
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... Upper order address lines are used only for 20-bit address width. 3: Demultiplexing is only required when multiple memory devices are accessed. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Flash and SRAM devices use different control signal combinations to implement Byte Select mode. JEDEC standard Flash memories require that a controller I/O port pin be connected to the memory’ ...
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... PIC18F87J10 FAMILY 8.6.4 16-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-4 and Figure 8-5. FIGURE 8-4: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
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... This signal only applies to table writes. See Section 7.1 “Table Reads and Table Writes”. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY will enable one byte of program memory for a portion of the instruction cycle, then BA0 will change and the second byte will be enabled to form the 16-bit instruc- tion word ...
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... PIC18F87J10 FAMILY 8.7.1 8-BIT MODE TIMING The presentation of control signals on the external memory bus is different for the various operating modes. Typical signal timing diagrams are shown in Figure 8-7 and Figure 8-8. FIGURE 8-7: EXTERNAL MEMORY BUS TIMING FOR TBLRD (EXTENDED MICROCONTROLLER MODE) ...
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... Microchip Technology Inc. PIC18F87J10 FAMILY In Sleep and Idle modes, the microcontroller core does not need to access data; bus operations are suspended. The state of the external bus is frozen, with ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 106 © 2009 Microchip Technology Inc. ...
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... Hardware Multiply Without Hardware Multiply signed Hardware Multiply Without Hardware Multiply unsigned Hardware Multiply Without Hardware Multiply signed Hardware Multiply © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY EXAMPLE 9- UNSIGNED MULTIPLY ROUTINE MOVF ARG1 MULWF ARG2 ; ARG1 * ARG2 -> ; PRODH:PRODL EXAMPLE 9-2: ...
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... PIC18F87J10 FAMILY Example 9-3 shows the sequence unsigned multiplication. Equation 9-1 shows the algorithm that is used. The 32-bit result is stored in four registers (RES3:RES0). EQUATION 9- UNSIGNED MULTIPLICATION ALGORITHM ARG1H:ARG1L • ARG2H:ARG2L RES3:RES0 = 16 (ARG1H • ARG2H • (ARG1H • ARG2L • (ARG1L • ARG2H • 2 (ARG1L • ...
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... INTERRUPTS Members of the PIC18F87J10 family of devices have multiple interrupt sources and an interrupt priority feature that allows most interrupt sources to be assigned a high-priority level or a low-priority level. The high-priority interrupt vector is at 0008h and the low-priority interrupt vector is at 0018h. High-priority interrupt events will interrupt any low-priority interrupts that may be in progress ...
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... PIC18F87J10 FAMILY FIGURE 10-1: PIC18F87J10 FAMILY INTERRUPT LOGIC PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<7, 0> PIE3<7, 0> IPR3<7, 0> High-Priority Interrupt Generation Low-Priority Interrupt Generation PIR1<7:0> PIE1<7:0> IPR1<7:0> PIR2<7:6, 3:0> PIE2<7:6, 3:0> IPR2<7:6, 3:0> PIR3<7, 0> PIE3<7, 0> ...
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... Note 1: A mismatch condition will continue to set this bit. Reading PORTB will end the mismatch condition and allow the bit to be cleared. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Note: Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit ...
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... PIC18F87J10 FAMILY REGISTER 10-2: INTCON2: INTERRUPT CONTROL REGISTER 2 R/W-1 R/W-1 R/W-1 RBPU INTEDG0 INTEDG1 bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 RBPU: PORTB Pull-up Enable bit 1 = All PORTB pull-ups are disabled 0 = PORTB pull-ups are enabled by individual port latch values ...
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... Interrupt flag bits are set when an interrupt condition occurs regardless of the state of its corresponding enable bit or the global interrupt enable bit. User software should ensure the appropriate interrupt flag bits are clear prior to enabling an interrupt. This feature allows for software polling. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-0 R/W-0 ...
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... PIC18F87J10 FAMILY 10.2 PIR Registers The PIR registers contain the individual flag bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Request (Flag) registers (PIR1, PIR2, PIR3). REGISTER 10-4: PIR1: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 1 ...
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... No TMR1/TMR3 register capture occurred Compare mode TMR1/TMR3 register compare match occurred (must be cleared in software TMR1 or TMR3 register compare match occurred PWM mode: Unused in this mode. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY U-0 R/W-0 U-0 — BCL1IF — Unimplemented bit, read as ‘0’ ...
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... PIC18F87J10 FAMILY REGISTER 10-6: PIR3: PERIPHERAL INTERRUPT REQUEST (FLAG) REGISTER 3 R/W-0 R/W-0 R-0 SSP2IF BCL2IF RC2IF bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IF: Master Synchronous Serial Port 2 Interrupt Flag bit 1 = The transmission/reception is complete (must be cleared in software) ...
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... Enables the TMR2 to PR2 match interrupt 0 = Disables the TMR2 to PR2 match interrupt bit 0 TMR1IE: TMR1 Overflow Interrupt Enable bit 1 = Enables the TMR1 overflow interrupt 0 = Disables the TMR1 overflow interrupt © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-0 R/W-0 TX1IE SSP1IE CCP1IE U = Unimplemented bit, read as ‘ ...
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... PIC18F87J10 FAMILY REGISTER 10-8: PIE2: PERIPHERAL INTERRUPT ENABLE REGISTER 2 R/W-0 R/W-0 U-0 OSCFIE CMIE — bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 OSCFIE: Oscillator Fail Interrupt Enable bit 1 = Enabled 0 = Disabled bit 6 CMIE: Comparator Interrupt Enable bit ...
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... Disabled bit 1 CCP4IE: CCP4 Interrupt Enable bit 1 = Enabled 0 = Disabled bit 0 CCP3IE: ECCP3 Interrupt Enable bit 1 = Enabled 0 = Disabled © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R-0 R/W-0 R/W-0 TX2IE TMR4IE CCP5IE U = Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared R/W-0 R/W-0 ...
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... PIC18F87J10 FAMILY 10.4 IPR Registers The IPR registers contain the individual priority bits for the peripheral interrupts. Due to the number of peripheral interrupt sources, there are three Peripheral Interrupt Priority registers (IPR1, IPR2, IPR3). Using the priority bits requires that the Interrupt Priority Enable (IPEN) bit be set ...
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... TMR3IP: TMR3 Overflow Interrupt Priority bit 1 = High priority 0 = Low priority bit 0 CCP2IP: ECCP2 Interrupt Priority bit 1 = High priority 0 = Low priority © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY U-0 R/W-1 U-0 — BCL1IP — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared ...
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... PIC18F87J10 FAMILY REGISTER 10-12: IPR3: PERIPHERAL INTERRUPT PRIORITY REGISTER 3 R/W-1 R/W-1 R/W-1 SSP2IP BCL2IP RC2IP bit 7 Legend Readable bit W = Writable bit -n = Value at POR ‘1’ = Bit is set bit 7 SSP2IP: Master Synchronous Serial Port 2 Interrupt Priority bit 1 = High priority 0 = Low priority bit 6 ...
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... For details of bit operation, see Register 4-1. bit 1 POR: Power-on Reset Status bit For details of bit operation, see Register 4-1. bit 0 BOR: Brown-out Reset Status bit For details of bit operation, see Register 4-1. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-1 R-1 R Unimplemented bit, read as ‘0’ ...
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... PIC18F87J10 FAMILY 10.6 INTx Pin Interrupts External interrupts on the RB0/INT0, RB1/INT1, RB2/INT2 and RB3/INT3 pins are edge-triggered. If the corresponding INTEDGx bit in the INTCON2 register is set (= 1), the interrupt is triggered by a rising edge; if the bit is clear, the trigger is on the falling edge. When a valid edge appears on the RBx/INTx pin, the corresponding flag bit, INTxIF, is set ...
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... RD TRIS Port © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 11.1 I/O Port Pin Capabilities When developing an application, the capabilities of the port pins must be considered. Outputs on some pins have higher output drive strength than others. Similarly, some pins can tolerate higher than V 11 ...
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... PIC18F87J10 FAMILY 11.1.2 INPUT PINS AND VOLTAGE CONSIDERATIONS The voltage tolerance of pins used as device inputs is dependent on the pin’s input function. Pins that are used as digital only inputs are able to handle DC voltages up to 5.5V, a level typical for digital logic circuits. In contrast, ...
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... TRISA — — ADCON1 — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTA. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATA<0> data output; not affected by analog input. I TTL PORTA<0> data input; disabled when analog input enabled. ...
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... PIC18F87J10 FAMILY 11.3 PORTB, TRISB and LATB Registers PORTB is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISB. Setting a TRISB bit (= 1) will make the corresponding PORTB pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISB bit (= 0) will make the corresponding PORTB pin an output (i ...
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... Alternate assignment for ECCP2/P2A when the CCP2MX Configuration bit is cleared (Extended Microcontroller mode, 80-pin devices only); default assignment is RC1. 2: All other pin functions are disabled when ICSP or ICD are enabled. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATB< ...
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... PIC18F87J10 FAMILY TABLE 11-6: SUMMARY OF REGISTERS ASSOCIATED WITH PORTB Name Bit 7 Bit 6 PORTB RB7 RB6 LATB LATB7 LATB6 TRISB TRISB7 TRISB6 INTCON GIE/GIEH PEIE/GIEL TMR0IE INTCON2 RBPU INTEDG0 INTEDG1 INTEDG2 INTEDG3 TMR0IP INTCON3 INT2IP INT1IP Legend: Shaded cells are not used by PORTB. ...
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... TRIS bit to make a pin an input. The user should refer to the corresponding peripheral section for the correct TRIS bit settings. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Note: These pins are configured as digital inputs on any device Reset. ...
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... PIC18F87J10 FAMILY TABLE 11-7: PORTC FUNCTIONS TRIS Pin Name Function I/O Setting RC0/T1OSO/ RC0 O 0 T13CKI I 1 T1OSO O x T13CKI I 1 RC1/T1OSI/ RC1 O 0 ECCP2/P2A I 1 T1OSI I x (1) ECCP2 (1) P2A O 0 RC2/ECCP1/ RC2 O 0 P1A I 1 ECCP1 P1A O 0 RC3/SCK1/ RC3 ...
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... TABLE 11-8: SUMMARY OF REGISTERS ASSOCIATED WITH PORTC Name Bit 7 Bit 6 PORTC RC7 RC6 LATC LATC7 LATBC6 TRISC TRISC7 TRISC6 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 RC5 RC4 RC3 RC2 LATC5 LATCB4 LATC3 LATC2 TRISC5 TRISC4 TRISC3 ...
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... PIC18F87J10 FAMILY 11.5 PORTD, TRISD and LATD Registers PORTD is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISD. Setting a TRISD bit (= 1) will make the corresponding PORTD pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISD bit (= 0) will make the corresponding PORTD pin an output (i ...
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... Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option). Note 1: External memory interface I/O takes priority over all other digital and PSP I/O. 2: Available on 80-pin devices only. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATD<0> data output PORTD< ...
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... PIC18F87J10 FAMILY TABLE 11-9: PORTD FUNCTIONS (CONTINUED) TRIS Pin Name Function Setting RD6/AD6/ RD6 0 PSP6/SCK2/ 1 SCL2 (2) AD6 x x PSP6 x x SCK2 0 1 SCL2 0 1 RD7/AD7/ RD7 0 PSP7/SS2 1 (2) AD7 x x PSP7 x x SS2 x Legend: PWR = Power Supply Output Input, I Output Schmitt Buffer Input, TTL = TTL Buffer Input Don’t care (TRIS bit does not affect port direction or is overridden for this option) ...
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... The pull-ups are disabled on any device Reset. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY PORTE is also multiplexed with Enhanced PWM outputs B and C for ECCP1 and ECCP3 and outputs B, C and D for ECCP2. For all devices, their default assignments are on PORTE< ...
Page 140
... PIC18F87J10 FAMILY TABLE 11-11: PORTE FUNCTIONS TRIS Pin Name Function Setting RE0/AD8/RD/ RE0 0 P2D 1 (3) AD8 P2D 0 RE1/AD9/WR/ RE1 0 P2C 1 (3) AD9 P2C 0 RE2/AD10/CS/ RE2 0 P2B 1 (3) AD10 P2B 0 RE3/AD11/ RE3 0 P3C 1 (3) AD11 x x (1) P3C 0 RE4/AD12/ RE4 0 P3B 1 (3) AD12 ...
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... LATE7 LATE6 TRISE TRISE7 TRISE6 PORTG RDPU REPU Legend: Shaded cells are not used by PORTE. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATE<6> data output PORTE<6> data input. O DIG External memory interface, address/data bit 14 output. ...
Page 142
... PIC18F87J10 FAMILY 11.7 PORTF, LATF and TRISF Registers PORTF is a 7-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISF. Setting a TRISF bit (= 1) will make the corresponding PORTF pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISF bit (= 0) will make the corresponding PORTF pin an output (i ...
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... CMCON C2OUT C1OUT CVRCON CVREN CVROE Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTF. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATF<1> data output; not affected by analog input PORTF<1> data input; disabled when analog input enabled. ...
Page 144
... PIC18F87J10 FAMILY 11.8 PORTG, TRISG and LATG Registers PORTG is a 5-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISG. Setting a TRISG bit (= 1) will make the corresponding PORTG pin an input (i.e., put the corresponding output driver in a high-impedance mode). Clearing a TRISG bit (= 0) will make the corresponding PORTG pin an output (i ...
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... TRISG — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by PORTG. Note 1: Unimplemented on 64-pin devices, read as ‘0’. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O Type DIG LATG<0> data output PORTG<0> data input. DIG CCP3 compare and PWM output ...
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... PIC18F87J10 FAMILY 11.9 PORTH, LATH and TRISH Registers Note: PORTH is available only on 80-pin devices. PORTH is an 8-bit wide, bidirectional I/O port. The cor- responding Data Direction register is TRISH. Setting a TRISH bit (= 1) will make the corresponding PORTH pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
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... Bit 6 PORTH RH7 RH6 LATH LATH7 LATH6 TRISH TRISH7 TRISH6 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O Type DIG LATH<0> data output. ST PORTH<0> data input. DIG External memory interface, address line 16. Takes priority over port data. DIG LATH<1> data output. ...
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... PIC18F87J10 FAMILY 11.10 PORTJ, TRISJ and LATJ Registers Note: PORTJ is available only on 80-pin devices. PORTJ is an 8-bit wide, bidirectional port. The corre- sponding Data Direction register is TRISJ. Setting a TRISJ bit (= 1) will make the corresponding PORTJ pin an input (i.e., put the corresponding output driver in a high-impedance mode) ...
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... LATJ LATJ7 LATJ6 TRISJ TRISJ7 TRISJ6 TRISJ5 PORTG RDPU REPU Legend: Shaded cells are not used by PORTJ. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY I/O I/O Type O DIG LATJ<0> data output PORTJ<0> data input. O DIG External memory interface address latch enable control output; takes priority over digital I/O ...
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... PIC18F87J10 FAMILY 11.11 Parallel Slave Port PORTD can also function as an 8-bit wide Parallel Slave Port, or microprocessor port, when control bit, PSPMODE (PSPCON<4>), is set asynchronously readable and writable by the external world through RD control input pin (RE0/RD) and WR control input pin (RE1/WR). ...
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... General Purpose I/O mode bit 3-0 Unimplemented: Read as ‘0’ FIGURE 11-3: PARALLEL SLAVE PORT WRITE WAVEFORMS PORTD<7:0> IBF OBF PSPIF © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 U-0 PSPMODE — Unimplemented bit, read as ‘0’ ‘0’ = Bit is cleared U-0 U-0 U-0 — ...
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... PIC18F87J10 FAMILY FIGURE 11-4: PARALLEL SLAVE PORT READ WAVEFORMS PORTD<7:0> IBF OBF PSPIF TABLE 11-21: REGISTERS ASSOCIATED WITH PARALLEL SLAVE PORT Name Bit 7 Bit 6 PORTD RD7 RD6 LATD LATD7 LATD6 TRISD TRISD7 TRISD6 PORTE RE7 RE6 LATE LATE7 LATE6 TRISE TRISE7 ...
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... Prescale value 000 = 1:2 Prescale value © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY The T0CON register (Register 12-1) controls all aspects of the module’s operation, including the prescale selection both readable and writable. A simplified block diagram of the Timer0 module in 8-bit mode is shown in Figure 12-1 ...
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... PIC18F87J10 FAMILY 12.1 Timer0 Operation Timer0 can operate as either a timer or a counter. The mode is selected with the T0CS bit (T0CON<5>). In Timer mode (T0CS = 0), the module increments on every clock by default unless a different prescaler value is selected (see Section 12.3 “Prescaler”). If the TMR0 register is written to, the increment is inhibited for the following two instruction cycles ...
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... T08BIT TRISA — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by Timer0. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 12.3.1 SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software control and can be changed “on-the-fly” during program execution ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 154 © 2009 Microchip Technology Inc. ...
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... TMR1ON: Timer1 On bit 1 = Enables Timer1 0 = Stops Timer1 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY A simplified block diagram of the Timer1 module is shown in Figure 13-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 13-2. The module incorporates its own low-power oscillator to provide an additional clocking option ...
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... PIC18F87J10 FAMILY 13.1 Timer1 Operation Timer1 can operate in one of these modes: • Timer • Synchronous Counter • Asynchronous Counter The operating mode is determined by the clock select bit, TMR1CS (T1CON<1>). When TMR1CS is cleared (= 0), Timer1 increments on every internal instruction FIGURE 13-1: TIMER1 BLOCK DIAGRAM ...
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... PIC18F87J10 27 pF T1OSI XTAL 32.768 kHz T1OSO Note: See the Notes with Table 13-1 for additional information about capacitor selection. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY TABLE 13-1: CAPACITOR SELECTION FOR THE TIMER OSCILLATOR Oscillator Freq. C1 Type ( kHz 27 pF Note 1: Microchip suggests these values as a starting point in validating the oscillator circuit ...
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... PIC18F87J10 FAMILY 13.3.3 TIMER1 OSCILLATOR LAYOUT CONSIDERATIONS The Timer1 oscillator circuit draws very little power during operation. Due to the low-power nature of the oscillator, it may also be sensitive to rapidly changing signals in close proximity. The oscillator circuit, shown in Figure 13-3, should be located as close as possible to the microcontroller. ...
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... T1CON RD16 T1RUN T1CKPS1 T1CKPS0 T1OSCEN T1SYNC Legend: Shaded cells are not used by the Timer1 module. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY ; Preload TMR1 register pair ; for 1 second overflow ; Configure for external clock, ; Asynchronous operation, external oscillator ; Initialize timekeeping registers ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 160 © 2009 Microchip Technology Inc. ...
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... Timer2 is off bit 1-0 T2CKPS<1:0>: Timer2 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 14.1 Timer2 Operation In normal operation, TMR2 is incremented from 00h on each clock (F /4). A 4-bit counter/prescaler on the OSC clock input gives direct input, divide-by-4 and divide-by-16 prescale options ...
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... PIC18F87J10 FAMILY 14.2 Timer2 Interrupt Timer2 can also generate an optional device interrupt. The Timer2 output signal (TMR2 to PR2 match) pro- vides the input for the 4-bit output counter/postscaler. This counter generates the TMR2 match interrupt flag which is latched in TMR2IF (PIR1<1>). The interrupt is enabled by setting the TMR2 Match Interrupt Enable bit, TMR2IE (PIE1< ...
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... TMR3ON: Timer3 On bit 1 = Enables Timer3 0 = Stops Timer3 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY A simplified block diagram of the Timer3 module is shown in Figure 15-1. A block diagram of the module’s operation in Read/Write mode is shown in Figure 15-2. The Timer3 module is controlled through the T3CON register (Register 15-1). It also selects the clock source options for the CCP and ECCP modules ...
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... PIC18F87J10 FAMILY 15.1 Timer3 Operation Timer3 can operate in one of three modes: • Timer • Synchronous Counter • Asynchronous Counter FIGURE 15-1: TIMER3 BLOCK DIAGRAM Timer1 Oscillator T1OSO/T13CKI T1OSI (1) T1OSCEN T3CKPS<1:0> T3SYNC TMR3ON CCPx Special Event Trigger CCPx Select from T3CON<6,3> Note 1: When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off to eliminate power drain. ...
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... T3CCP2 T3CKPS1 T3CKPS0 T3CCP1 Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by the Timer3 module. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 15.4 Timer3 Interrupt The TMR3 register pair (TMR3H:TMR3L) increments from 0000h to FFFFh and overflows to 0000h. The Timer3 interrupt, if enabled, is generated on overflow and is latched in interrupt flag bit, TMR3IF (PIR2< ...
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... PIC18F87J10 FAMILY NOTES: DS39663F-page 166 © 2009 Microchip Technology Inc. ...
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... T4CKPS<1:0>: Timer4 Clock Prescale Select bits 00 = Prescaler Prescaler Prescaler is 16 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 16.1 Timer4 Operation Timer4 can be used as the PWM time base for the PWM mode of the CCP module. The TMR4 register is readable and writable and is cleared on any device Reset ...
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... PIC18F87J10 FAMILY 16.2 Timer4 Interrupt The Timer4 module has an 8-Bit Period register, PR4, which is both readable and writable. Timer4 increments from 00h until it matches PR4 and then resets to 00h on the next increment cycle. The PR4 register is initialized to FFh upon Reset. FIGURE 16-1: TIMER4 BLOCK DIAGRAM T4OUTPS< ...
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... CAPTURE/COMPARE/PWM (CCP) MODULES Members of the PIC18F87J10 family of devices all have a total of five CCP (Capture/Compare/PWM) modules. Two of these (CCP4 and CCP5) implement standard Capture, Compare and Pulse-Width Modulation (PWM) modes and are discussed in this section. The other three modules (ECCP1, ECCP2, ...
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... PIC18F87J10 FAMILY 17.1 CCP Module Configuration Each Capture/Compare/PWM module is associated with a control register (generically, CCPxCON) and a data register (CCPRx). The data register, in turn, is comprised of two 8-bit registers: CCPRxL (low byte) and CCPRxH (high byte). All registers are both readable and writable. ...
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... Q1:Q4 CCP5CON<3:0> CCP5 pin Prescaler ÷ © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 17.2.3 SOFTWARE INTERRUPT When the Capture mode is changed, a false capture interrupt may be generated. The user should keep the CCPxIE interrupt enable bit clear to avoid false interrupts. The interrupt flag bit, CCPxIF, should also be cleared following any such change in operating mode ...
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... PIC18F87J10 FAMILY 17.3 Compare Mode In Compare mode, the 16-Bit CCPRx register value is constantly compared against either the TMR1 or TMR3 register pair value. When a match occurs, the CCPx pin can be: • driven high • driven low • toggled (high-to-low or low-to-high) • remains unchanged (that is, reflects the state of ...
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... Capture/Compare/PWM Register 5 Low Byte CCPR5H Capture/Compare/PWM Register 5 High Byte CCP4CON — — CCP5CON — — Legend: — = unimplemented, read as ‘0’. Shaded cells are not used by capture/compare, Timer1 or Timer3. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Bit 5 Bit 4 Bit 3 Bit 2 INT0IE RBIE TMR0IF — ...
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... PIC18F87J10 FAMILY 17.4 PWM Mode In Pulse-Width Modulation (PWM) mode, the CCPx pin produces 10-bit resolution PWM output. Since the CCP4 and CCP5 pins are multiplexed with a PORTG data latch, the appropriate TRISG bit must be cleared to make the CCP4 or CCP5 pin an output. ...
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... Timer Prescaler (1, 4, 16) PR2 Value FFh Maximum Resolution (bits) © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 17.4.3 SETUP FOR PWM OPERATION The following steps should be taken when configuring the CCP module for PWM operation: 1. Set the PWM period by writing to the PR2 (PR4) register ...
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... PIC18F87J10 FAMILY TABLE 17-4: REGISTERS ASSOCIATED WITH PWM, TIMER2 AND TIMER4 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN — PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR3 SSP2IF BCL2IF PIE3 SSP2IE BCL2IE IPR3 SSP2IP BCL2IP TRISG — — ...
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... ENHANCED CAPTURE/ COMPARE/PWM (ECCP) MODULE In the PIC18F87J10 family of devices, three of the CCP modules are implemented as standard CCP modules with Enhanced PWM capabilities. These include the provision for output channels, user-selectable polarity, dead-band control and automatic shutdown and restart. The Enhanced features are discussed in detail in Section 18.4 “ ...
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... PIC18F87J10 FAMILY 18.1 ECCP Outputs and Configuration Each of the Enhanced CCP modules may have up to four PWM outputs, depending on the selected operating mode. These outputs, designated PxA through PxD, are multiplexed with various I/O pins. Some ECCP pin assignments are constant, while others change based on device configuration ...
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... Dual PWM 10xx 11xx Quad PWM x1xx 11xx Legend Don’t care. Shaded cells indicate pin assignments not used by ECCP2 in a given mode. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY RC2 RE6 RE5 All PIC18F6XJ10/6XJ15 Devices: RE6 RE5 P1A ...
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... PIC18F87J10 FAMILY TABLE 18-3: PIN CONFIGURATIONS FOR ECCP3 CCP3CON ECCP Mode Configuration Compatible CCP ECCP3 00xx 11xx Dual PWM 10xx 11xx Quad PWM x1xx 11xx PIC18F8XJ10/8XJ15 Devices, ECCPMX = 0, Microcontroller mode: Compatible CCP ECCP3 00xx 11xx Dual PWM 10xx 11xx Quad PWM ...
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... Note: The 8-bit timer TMR2 register is concatenated with the 2-bit internal Q clock bits of the prescaler, to create the 10-bit time base. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY waveforms do not exactly match the standard PWM waveforms, but are instead offset by one full instruction cycle ( ...
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... PIC18F87J10 FAMILY 18.4.2 PWM DUTY CYCLE The PWM duty cycle is specified by writing to the CCPR1L register and to the CCP1CON<5:4> bits 10-bit resolution is available. The CCPR1L contains the eight MSbs and the CCP1CON<5:4> contains the two LSbs. This 10-bit value is represented by CCPR1L:CCP1CON<5:4>. The PWM duty cycle is ...
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... Duty Cycle = T * (CCPR1L<7:0>:CCP1CON<5:4>) * (TMR2 Prescale Value) OSC • Delay = (ECCP1DEL<6:0>) OSC Note 1: The dead-band delay is programmed using the ECCP1DEL register (Section 18.4.6 “Programmable Dead-Band Delay”). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 0 Duty Cycle Period (1) (1) Delay Delay 0 ...
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... PIC18F87J10 FAMILY 18.4.4 HALF-BRIDGE MODE In the Half-Bridge Output mode, two pins are used as outputs to drive push-pull loads. The PWM output signal is output on the P1A pin, while the complemen- tary PWM output signal is output on the P1B pin (Figure 18-4). This mode can be used for half-bridge ...
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... Note 1: At this time, the TMR2 register is equal to the PR2 register. Note 2: The output signal is shown as active-high. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY P1A, P1B, P1C and P1D outputs are multiplexed with the port pins as described in Table 18-1, Table 18-2 and Table 18-3. The corresponding TRIS bits must be cleared to make the P1A, P1B, P1C and P1D pins outputs ...
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... PIC18F87J10 FAMILY FIGURE 18-7: EXAMPLE OF FULL-BRIDGE APPLICATION PIC18F87J10 P1A P1B P1C P1D 18.4.5.1 Direction Change in Full-Bridge Mode In the Full-Bridge Output mode, the P1M1 bit in the CCP1CON register allows users to control the forward/ reverse direction. When the application firmware changes this direction control bit, the module will assume the new direction on the next PWM cycle ...
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... Note 1: All signals are shown as active-high the turn-on delay of power switch, QC, and its driver the turn-off delay of power switch, QD, and its driver. OFF © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY (1) Period DC , depending on the Timer2 prescaler value. The modulated P1B and P1D signals OSC Forward Period t1 ...
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... PIC18F87J10 FAMILY 18.4.6 PROGRAMMABLE DEAD-BAND DELAY In half-bridge applications, where all power switches are modulated at the PWM frequency at all times, the power switches normally require more time to turn off than to turn on. If both the upper and lower power switches are switched at the same time (one turned on ...
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... Independent of the P1RSEN bit setting, if the auto-shutdown source is one of the comparators, the shutdown condition is a level. The ECCP1ASE bit cannot be cleared as long as the cause of the shutdown persists. © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-0 R/W-0 ECCPxAS0 PSSxAC1 PSSxAC0 U = Unimplemented bit, read as ‘ ...
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... PIC18F87J10 FAMILY The P1A, P1B, P1C and P1D output latches may not be in the proper states when the PWM module is initialized. Enabling the PWM pins for output at the same time as the ECCP1 module may cause damage to the applica- tion circuit. The ECCP1 module must be enabled in the ...
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... Select the shutdown states of the PWM output pins using the PSSxAC<1:0> and PSSxBD<1:0> bits. • Set the ECCPxASE bit (ECCPxAS<7>). © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY 8. If auto-restart operation is required, set the PxRSEN bit (ECCPxDEL<7>). 9. Configure and start TMRx (TMR2 or TMR4): • ...
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... PIC18F87J10 FAMILY TABLE 18-5: REGISTERS ASSOCIATED WITH ECCP MODULES AND TIMER1 TO TIMER4 Name Bit 7 Bit 6 INTCON GIE/GIEH PEIE/GIEL RCON IPEN — PIR1 PSPIF ADIF PIE1 PSPIE ADIE IPR1 PSPIP ADIP PIR2 OSCFIF CMIF PIE2 OSCFIE CMIE IPR2 OSCFIP CMIP PIR3 SSP2IF ...
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... Master mode • Multi-Master mode • Slave mode (with address masking for both 10-bit and 7-bit addressing) All members of the PIC18F87J10 family have two MSSP modules, designated as MSSP1 and MSSP2. Each module operates independently of the other. Note: Throughout this section, generic refer- ...
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... PIC18F87J10 FAMILY 19.3.1 REGISTERS Each MSSP module has four registers for SPI mode operation. These are: • MSSP Control Register 1 (SSPxCON1) • MSSP Status Register (SSPxSTAT) • Serial Receive/Transmit Buffer Register (SSPxBUF) • MSSP Shift Register (SSPxSR) – Not directly accessible SSPxCON1 and SSPxSTAT are the control and status registers in SPI mode operation ...
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... In Master mode, the overflow bit is not set since each new reception (and transmission) is initiated by writing to the SSPxBUF register. 2: When enabled, these pins must be properly configured as input or output. 3: Bit combinations not specifically listed here are either reserved or implemented in I © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY R/W-0 R/W-0 R/W-0 CKP SSPM3 SSPM2 U = Unimplemented bit, read as ‘ ...
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... PIC18F87J10 FAMILY 19.3.2 OPERATION When initializing the SPI, several options need to be specified. This is done by programming the appropriate control bits (SSPxCON1<5:0> and SSPxSTAT<7:6>). These control bits allow the following to be specified: • Master mode (SCKx is the clock output) • Slave mode (SCKx is the clock input) • ...
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... Shift Register (SSPxSR) LSb MSb PROCESSOR 1 © 2009 Microchip Technology Inc. PIC18F87J10 FAMILY Any serial port function that is not desired may be overridden by programming the corresponding Data Direction (TRIS) register to the opposite value. 19.3.4 TYPICAL CONNECTION Figure 19-2 shows a typical connection between two microcontrollers ...
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... PIC18F87J10 FAMILY 19.3.5 MASTER MODE The master can initiate the data transfer at any time because it controls the SCKx. The master determines when the slave (Processor 1, Figure 19- broadcast data by the software protocol. In Master mode, the data is transmitted/received as soon as the SSPxBUF register is written to. If the SPI is only going to receive, the SDOx output could be dis- abled (programmed as an input) ...