PIC16F72-I/SP Microchip Technology, PIC16F72-I/SP Datasheet - Page 490

• Manufacturer Part Number: PIC16F72-I/SP
• Description: IC PIC MCU FLASH 2KX14 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 5 Channel
• Data Rom Size: 8 B
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
26.3.1
26.3.2
DS31026A-page 26-6
Config. bits
OPTION_REG
Legend: Shaded cells are not used by the Watchdog Timer.
Name
WDT Period
WDT Programming Considerations
MPEEN
RBPU
Bit 7
The WDT has a nominal time-out period of 18 ms, (with no postscaler). The time-out period var-
ies with temperature, V
time-outs are desired, a postscaler with a division ratio of up to 1:128 can be assigned to the
WDT, under software control, by writing to the OPTION_REG register. Thus, time-out periods of
up to 2.3 seconds can be realized.
The
and prevent it from timing out and generating a device RESET.
The TO bit in the STATUS register will be cleared upon a Watchdog Timer time-out (WDT Reset
and WDT wake-up).
It should also be taken in account that under worst case conditions (V
ture = Maximum, maximum WDT postscaler) it may take several seconds before a WDT time-out
occurs.
Table 26-1: Summary of Watchdog Timer Registers
Note:
CLRWDT
INTEDG
BODEN
Bit 6
When the postscaler is assigned to the WDT, always execute a CLRWDT instruction
before changing the postscale value, otherwise a WDT reset may occur.
and
SLEEP
DD
instructions clear the WDT and the postscaler (if assigned to the WDT)
T0CS
Bit 5
CP1
and process variations from part to part (see DC specs). If longer
T0SE
Bit 4
CP0
PWRTE
Bit 3
PSA
WDTE
Bit 2
PS2
1997 Microchip Technology Inc.
DD
FOSC1
= Minimum, Tempera-
Bit 1
PS1
FOSC0
Bit 0
PS0