PIC16F72-I/SP Microchip Technology, PIC16F72-I/SP Datasheet - Page 230

• Manufacturer Part Number: PIC16F72-I/SP
• Description: IC PIC MCU FLASH 2KX14 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 5 Channel
• Data Rom Size: 8 B
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

PICmicro MID-RANGE MCU FAMILY
15.3.4
DS31015A-page 15-10
SCK (CKP = 0,
SCK (CKP = 0,
SCK (CKP = 1,
SCK (CKP = 1,
SDO (CKE = 0)
SDO (CKE = 1)
SDI (SMP = 0)
Input
Sample (SMP = 0)
SDI (SMP = 1)
Input
Sample (SMP = 1)
Write to
SSPBUF
SSPIF
SSPSR to
SSPBUF
CKE = 1)
CKE = 0)
CKE = 0)
CKE = 1)
Master Operation
The master can initiate the data transfer at any time because it controls the SCK. The master
determines when the slave (Processor 2) is to broadcast data by the software protocol.
In master mode the data is transmitted/received as soon as the SSPBUF register is written to. If
the SPI is only going to receive, the SDO output could be disabled (programmed as an input).
The SSPSR register will continue to shift in the signal present on the SDI pin at the programmed
clock rate. As each byte is received, it will be loaded into the SSPBUF register as if a normal
received byte (interrupts and status bits appropriately set). This could be useful in receiver appli-
cations as a “line activity monitor” mode.
The clock polarity is selected by appropriately programming bit CKP (SSPCON<4>). This then
would give waveforms for SPI communication as shown in
Figure 15-5
user programmable to be one of the following:
• F
• F
• F
• Timer2 output/2
This allows a maximum data rate of 5 Mbps (at 20 MHz).
Figure 15-3:
bit7
OSC
OSC
OSC
bit7
bit7
/4 (or T
/16 (or 4 • T
/64 (or 16 • T
bit7
where the MSb is transmitted first. In master mode, the SPI clock rate (bit rate) is
CY
bit6
bit6
SPI Mode Waveform, Master Mode
)
CY
CY
)
)
bit5
bit5
bit4
bit4
bit3
bit3
bit2
bit2
bit1
bit1
Figure
1997 Microchip Technology Inc.
bit0
bit0
bit0
15-3,
bit0
Figure
Next Q4 cycle
after Q2
4 clock
modes
15-4, and