PIC16F72-I/SP Microchip Technology, PIC16F72-I/SP Datasheet - Page 109

• Manufacturer Part Number: PIC16F72-I/SP
• Description: IC PIC MCU FLASH 2KX14 28DIP
• Manufacturer: Microchip Technology
• Series: PIC® 16Fr

Specifications of PIC16F72-I/SP

• Program Memory Type: FLASH
• Program Memory Size: 3.5KB (2K x 14)
• Package / Case: 28-DIP (0.300", 7.62mm)
• Core Processor: PIC
• Core Size: 8-Bit
• Speed: 20MHz
• Connectivity: I²C, SPI
• Peripherals: Brown-out Detect/Reset, POR, PWM, WDT
• Number Of I /o: 22
• Ram Size: 128 x 8
• Voltage - Supply (vcc/vdd): 4 V ~ 5.5 V
• Data Converters: A/D 5x8b
• Oscillator Type: External
• Operating Temperature: -40°C ~ 85°C
• Processor Series: PIC16F
• Core: PIC
• Data Bus Width: 8 bit
• Data Ram Size: 128 B
• Interface Type: I2C, SPI, SSP
• Maximum Clock Frequency: 20 MHz
• Number Of Programmable I/os: 22
• Number Of Timers: 3
• Operating Supply Voltage: 2 V to 5.5 V
• Maximum Operating Temperature: + 85 C
• Mounting Style: Through Hole
• 3rd Party Development Tools: 52715-96, 52716-328, 52717-734
• Development Tools By Supplier: ICE2000, DM163022
• Minimum Operating Temperature: - 40 C
• On-chip Adc: 8 bit, 5 Channel
• Data Rom Size: 8 B
• Height: 3.3 mm
• Length: 34.67 mm
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 2 V
• Width: 7.24 mm
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Eeprom Size: -
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

1997 Microchip Technology Inc.
Example 6-4: RAM Initialization
Bank0_LP
;
; Next Bank (Bank1)
; (** ONLY REQUIRED IF DEVICE HAS A BANK1 **)
;
Bank1_LP
;
; Next Bank (Bank2)
; (** ONLY REQUIRED IF DEVICE HAS A BANK2 **)
;
Bank2_LP
;
; Next Bank (Bank3)
; (** ONLY REQUIRED IF DEVICE HAS A BANK3 **)
;
Bank3_LP
:
CLRF
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
BSF
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
MOVLW
MOVWF
CLRF
INCF
BTFSS
GOTO
Section 6. Memory Organization
STATUS
0x20
FSR
INDF0
FSR
FSR, 7
Bank0_LP
0xA0
FSR
INDF0
FSR
STATUS, C
Bank1_LP
STATUS, IRP
0x20
FSR
INDF0
FSR
FSR, 7
Bank2_LP
0xA0
FSR
INDF0
FSR
STATUS, C
Bank3_LP
; Clear STATUS register (Bank0)
; 1st address (in bank) of GPR area
; Move it to Indirect address register
; Clear GPR at address pointed to by FSR
; Next GPR (RAM) address
; End of current bank ? (FSR = 80h, C = 0)
; NO, clear next location
; 1st address (in bank) of GPR area
; Move it to Indirect address register
; Clear GPR at address pointed to by FSR
; Next GPR (RAM) address
; End of current bank? (FSR = 00h, C = 1)
; NO, clear next location
; Select Bank2 and Bank3
;
; 1st address (in bank) of GPR area
; Move it to Indirect address register
; Clear GPR at address pointed to by FSR
; Next GPR (RAM) address
; End of current bank? (FSR = 80h, C = 0)
; NO, clear next location
; 1st address (in bank) of GPR area
; Move it to Indirect address register
; Clear GPR at address pointed to by FSR
; Next GPR (RAM) address
; End of current bank? (FSR = 00h, C = 1)
; NO, clear next location
; YES, All GPRs (RAM) is cleared
for Indirect addressing
DS31006A-page 6-15
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