PIC12C509A-04/SM Microchip Technology, PIC12C509A-04/SM Datasheet - Page 28
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PIC12C509A-04/SM
Manufacturer Part Number
PIC12C509A-04/SM
Description
IC MCU OTP 1KX12 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr
Datasheets
1.PIC12C508A-04SM.pdf
(113 pages)
2.PIC12C508A-04SM.pdf
(6 pages)
3.PIC12C508A-04SM.pdf
(16 pages)
4.PIC12C508A-04SM.pdf
(4 pages)
Specifications of PIC12C509A-04/SM
Core Size
8-Bit
Program Memory Size
1.5KB (1K x 12)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
41Byte
Cpu Speed
4MHz
No. Of Timers
1
Digital Ic Case Style
SOIC
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
41 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
DVMCPA, ICE2000
Minimum Operating Temperature
0 C
Package
8SOIJ
Device Core
PIC
Family Name
PIC12
Maximum Speed
4 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
Details
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
PIC12C509A-04/SM
Manufacturer:
MIC
Quantity:
1 485
Part Number:
PIC12C509A-04/SM
Manufacturer:
MIC
Quantity:
20 000
PIC12C5XX
6.2
An 8-bit counter is available as a prescaler for the
Timer0 module, or as a postscaler for the Watchdog
Timer (WDT), respectively (Section 8.6). For simplicity,
this counter is being referred to as “prescaler”
throughout this data sheet. Note that the prescaler
may be used by either the Timer0 module or the WDT,
but not both. Thus, a prescaler assignment for the
Timer0 module means that there is no prescaler for
the WDT, and vice-versa.
The
determine prescaler assignment and prescale ratio.
When assigned to the Timer0 module, all instructions
writing
MOVWF 1, BSF 1,x, etc.) will clear the prescaler.
When assigned to WDT, a CLRWDT instruction will
clear the prescaler along with the WDT. The prescaler
is neither readable nor writable. On a RESET, the
prescaler contains all '0's.
6.2.1
The prescaler assignment is fully under software control
(i.e., it can be changed “on the fly” during program
execution). To avoid an unintended device RESET, the
following instruction sequence (Example 6-1) must be
executed when changing the prescaler assignment from
Timer0 to the WDT.
FIGURE 6-5:
DS40139E-page 28
PSA
Note: T0CS, T0SE, PSA, PS2:PS0 are bits in the OPTION register.
to
Prescaler
SWITCHING PRESCALER ASSIGNMENT
WDT Enable bit
Watchdog
GP2/T0CKI
the
Timer
T
and
CY
Pin
( = Fosc/4)
BLOCK DIAGRAM OF THE TIMER0/WDT PRESCALER
TMR0
T0SE
PS2:PS0
register
0
1
bits
PSA
M
U
X
(e.g.,
(OPTION<3:0>)
0
1
T0CS
M
U
X
CLRF 1,
8-bit Prescaler
0
8 - to - 1MUX
Time-Out
8
MUX
WDT
1
0
1
PSA
EXAMPLE 6-1:
To change prescaler from the WDT to the Timer0
module, use the sequence shown in Example 6-2. This
sequence must be used even if the WDT is disabled. A
CLRWDT
switching the prescaler.
EXAMPLE 6-2:
CLRWDT
MOVLW
OPTION
M
U
X
1.CLRWDT
2.CLRF
3.MOVLW
4.OPTION
5.CLRWDT
6.MOVLW
7.OPTION
PSA
'xxxx0xxx'
PS2:PS0
instruction
TMR0
'00xx1111’b ;These 3 lines (5, 6, 7)
'00xx1xxx’b ;Set Postscaler to
Cycles
Sync
2
CHANGING PRESCALER
(TIMER0 WDT)
CHANGING PRESCALER
(WDT TIMER0)
should
1999 Microchip Technology Inc.
;Clear WDT
;Clear TMR0 & Prescaler
; desired
;PS<2:0> are 000 or 001
; are required only if
; desired WDT rate
;Clear WDT and
;prescaler
;Select TMR0, new
;prescale value and
;clock source
TMR0 reg
Data Bus
be
8
executed
before