PIC12C509A-04/SM Microchip Technology, PIC12C509A-04/SM Datasheet - Page 19

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PIC12C509A-04/SM

Manufacturer Part Number
PIC12C509A-04/SM
Description
IC MCU OTP 1KX12 8-SOIJ
Manufacturer
Microchip Technology
Series
PIC® 12Cr

Specifications of PIC12C509A-04/SM

Core Size
8-Bit
Program Memory Size
1.5KB (1K x 12)
Core Processor
PIC
Speed
4MHz
Peripherals
POR, WDT
Number Of I /o
5
Program Memory Type
OTP
Ram Size
41 x 8
Voltage - Supply (vcc/vdd)
3 V ~ 5.5 V
Oscillator Type
Internal
Operating Temperature
0°C ~ 70°C
Package / Case
8-SOIC (5.3mm Width), 8-SOP, 8-SOEIAJ
Controller Family/series
PIC12
No. Of I/o's
6
Ram Memory Size
41Byte
Cpu Speed
4MHz
No. Of Timers
1
Digital Ic Case Style
SOIC
Processor Series
PIC12C
Core
PIC
Data Bus Width
8 bit
Data Ram Size
41 B
Maximum Clock Frequency
4 MHz
Number Of Programmable I/os
5
Number Of Timers
8
Operating Supply Voltage
2.5 V to 5.5 V
Maximum Operating Temperature
+ 70 C
Mounting Style
SMD/SMT
3rd Party Development Tools
52715-96, 52716-328, 52717-734
Development Tools By Supplier
DVMCPA, ICE2000
Minimum Operating Temperature
0 C
Package
8SOIJ
Device Core
PIC
Family Name
PIC12
Maximum Speed
4 MHz
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
For Use With
XLT08SO-1 - SOCKET TRANSITION 8SOIC 150/208AC164312 - MODULE SKT FOR PM3 16SOICISPICR1 - ADAPTER IN-CIRCUIT PROGRAMMING309-1048 - ADAPTER 8-SOIC TO 8-DIP309-1047 - ADAPTER 8-SOIC TO 8-DIPAC124001 - MODULE SKT PROMATEII 8DIP/SOIC
Eeprom Size
-
Data Converters
-
Connectivity
-
Lead Free Status / Rohs Status
 Details

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
PIC12C509A-04/SM
Manufacturer:
MIC
Quantity:
1 485
Part Number:
PIC12C509A-04/SM
Manufacturer:
MIC
Quantity:
20 000
4.6
As a program instruction is executed, the Program
Counter (PC) will contain the address of the next
program instruction to be executed. The PC value is
increased by one every instruction cycle, unless an
instruction changes the PC.
For a GOTO instruction, bits 8:0 of the PC are provided
by the GOTO instruction word. The PC Latch (PCL) is
mapped to PC<7:0>. Bit 5 of the STATUS register
provides page information to bit 9 of the PC (Figure 4-
8).
For a CALL instruction, or any instruction where the
PCL is the destination, bits 7:0 of the PC again are
provided by the instruction word. However, PC<8>
does not come from the instruction word, but is always
cleared (Figure 4-8).
Instructions where the PCL is the destination, or
Modify PCL instructions, include MOVWF PC, ADDWF
PC, and BSF PC,5.
FIGURE 4-8:
CALL or Modify PCL Instruction
GOTO Instruction
Note:
1999 Microchip Technology Inc.
PC
PC
Program Counter
11
11
Because PC<8> is cleared in the CALL
instruction, or any Modify PCL instruction,
all subroutine calls or computed jumps are
limited to the first 256 locations of any pro-
gram memory page (512 words long).
7
7
10
10
9
STATUS
9
LOADING OF PC
BRANCH INSTRUCTIONS -
PIC12C5XX
STATUS
PA0
Reset to ‘0’
PA0
8 7
8 7
Instruction Word
Instruction Word
PCL
PCL
0
0
0
0
4.6.1
The Program Counter is set upon a RESET, which
means that the PC addresses the last location in the
last page i.e., the oscillator calibration instruction. After
executing MOVLW XX, the PC will roll over to location
00h, and begin executing user code.
The STATUS register page preselect bits are cleared
upon a RESET, which means that page 0 is pre-
selected.
Therefore, upon a RESET, a
automatically cause the program to jump to page 0
until the value of the page bits is altered.
4.7
PIC12C5XX devices have a 12-bit wide L.I.F.O.
hardware push/pop stack.
A CALL instruction will push the current value of stack
1 into stack 2 and then push the current program
counter value, incremented by one, into stack level 1. If
more than two sequential CALL’s are executed, only
the most recent two return addresses are stored.
A RETLW instruction will pop the contents of stack level
1 into the program counter and then copy stack level 2
contents into level 1. If more than two sequential
RETLW’s are executed, the stack will be filled with the
address previously stored in level 2. Note that the
W register will be loaded with the literal value specified
in the instruction. This is particularly useful for the
implementation of data look-up tables within the
program memory.
Upon any reset, the contents of the stack remain
unchanged, however the program counter (PCL) will
also be reset to 0.
Note 1: There are no STATUS bits to indicate
Note 2: There are no instructions mnemonics
Stack
EFFECTS OF RESET
stack overflows or stack underflow condi-
tions.
called PUSH or POP. These are actions
that occur from the execution of the CALL
and RETLW instructions.
PIC12C5XX
GOTO instruction will
DS40139E-page 19

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