C8051F326-TB Silicon Laboratories Inc, C8051F326-TB Datasheet - Page 98

• Manufacturer Part Number: C8051F326-TB
• Description: BOARD PROTOTYPING W/C8051F326
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F326-TB

• Contents: Board
• Processor To Be Evaluated: C8051F326/F327
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F326
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F326/7
12.7. Function Configuration and Control
The USB register POWER (Figure 12.8) is used to configure and control USB0 at the device level (enable/
disable, Reset/Suspend/Resume handling, etc.).
USB Reset: The USBRST bit (POWER.3) is set to ‘1’ by hardware when Reset signaling is detected on
the bus. Upon this detection, the following occur:
Writing a ‘1’ to the USBRST bit will generate an asynchronous USB0 reset. All USB registers are reset to
their default values following this asynchronous reset.
Suspend Mode: With Suspend Detection enabled (SUSEN = ‘1’), USB0 will enter Suspend Mode when
Suspend signaling is detected on the bus. An interrupt will be generated if enabled (SUSINTE = ‘1’). The
Suspend Interrupt Service Routine (ISR) should perform application-specific configuration tasks such as
disabling appropriate peripherals and/or configuring clock sources for low power modes. See Section
“10. Oscillators” on page 71 for more details on internal oscillator configuration, including the Suspend
mode feature of the internal oscillator.
USB0 exits Suspend mode when any of the following occur: (1) Resume signaling is detected or gener-
ated, (2) Reset signaling is detected, or (3) a device or USB reset occurs. If suspended, the internal oscil-
lator will exit Suspend mode upon any of the above listed events.
Resume Signaling: USB0 will exit Suspend mode if Resume signaling is detected on the bus. A Resume
interrupt will be generated upon detection if enabled (RESINTE = ‘1’). Software may force a Remote
Wakeup by writing ‘1’ to the RESUME bit (POWER.2). When forcing a Remote Wakeup, software should
write RESUME = ‘0’ to end Resume signaling 10-15 ms after the Remote Wakeup is initiated (RESUME =
‘1’).
ISO Update: When software writes ‘1’ to the ISOUP bit (POWER.7), the ISO Update function is enabled.
With ISO Update enabled, new packets written to an ISO IN endpoint will not be transmitted until a new
Start-Of-Frame (SOF) is received. If the ISO IN endpoint receives an IN token before a SOF, USB0 will
transmit a zero-length packet. When ISOUP = ‘1’, ISO Update is enabled for all ISO endpoints.
USB Enable: USB0 is disabled following a Power-On-Reset (POR). USB0 is enabled by clearing the
USBINH bit (POWER.4). Once written to ‘0’, the USBINH can only be set to ‘1’ by one of the following: (1)
a Power-On-Reset (POR), or (2) an asynchronous USB0 reset generated by writing ‘1’ to the USBRST bit
(POWER.3).
Software should perform all USB0 configuration before enabling USB0. The configuration sequence
should be performed as follows:
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1.
2.
3.
4.
5.
6.
Step 1. Select and enable the USB clock source.
Step 2. Reset USB0 by writing USBRST= ‘1’.
Step 3. Configure and enable the USB Transceiver.
Step 4. Perform any USB0 function configuration (interrupts, Suspend detect).
Step 5. Enable USB0 by writing USBINH = ‘0’.
The USB0 Address is reset (FADDR = 0x00).
Endpoint FIFOs are flushed.
Control/status registers are reset to 0x00 (E0CSR, EINCSRL, EINCSRH, EOUTCSRL, EOUTCSRH).
USB register INDEX is reset to 0x00.
All USB interrupts (excluding the Suspend interrupt) are enabled and their corresponding flags cleared.
A USB Reset interrupt is generated if enabled.
Rev. 1.1