C8051F326-TB Silicon Laboratories Inc, C8051F326-TB Datasheet - Page 102

• Manufacturer Part Number: C8051F326-TB
• Description: BOARD PROTOTYPING W/C8051F326
• Manufacturer: Silicon Laboratories Inc
• Type: MCUr

Specifications of C8051F326-TB

• Contents: Board
• Processor To Be Evaluated: C8051F326/F327
• Interface Type: USB
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• For Use With/related Products: C8051F326
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

C8051F326/7
102
Bits7–4: Unused. Read = 0000b. Write = don’t care.
Bit3:
Bit2:
Bit1:
Bit0:
Bits7–2: Unused. Read = 000000b. Write = don’t care.
Bit1:
Bit0:
R/W
Bit7
Bit7
—
USB Register Definition 12.14. IN1IE: USB0 IN Endpoint Interrupt Enable
—
R
USB Register Definition 12.13. CMINT: USB0 Common Interrupt
SOF: Start of Frame Interrupt
Set by hardware when a SOF token is received. This interrupt event is synthesized by hard-
ware: an interrupt will be generated when hardware expects to receive a SOF event, even if
the actual SOF signal is missed or corrupted.
This bit is cleared when software reads the CMINT register.
0: SOF interrupt inactive.
1: SOF interrupt active.
RSTINT: Reset Interrupt-pending Flag
Set by hardware when Reset signaling is detected on the bus.
This bit is cleared when software reads the CMINT register.
0: Reset interrupt inactive.
1: Reset interrupt active.
RSUINT: Resume Interrupt-pending Flag
Set by hardware when Resume signaling is detected on the bus while USB0 is in suspend
mode.
This bit is cleared when software reads the CMINT register.
0: Resume interrupt inactive.
1: Resume interrupt active.
SUSINT: Suspend Interrupt-pending Flag
When Suspend detection is enabled (bit SUSEN in register POWER), this bit is set by hard-
ware when Suspend signaling is detected on the bus. This bit is cleared when software
reads the CMINT register.
0: Suspend interrupt inactive.
1: Suspend interrupt active.
IN1E: IN Endpoint 1 Interrupt Enable
0: IN Endpoint 1 interrupt disabled.
1: IN Endpoint 1 interrupt enabled.
EP0E: Endpoint 0 Interrupt Enable
0: Endpoint 0 interrupt disabled.
1: Endpoint 0 interrupt enabled.
R/W
Bit6
Bit6
—
—
R
R/W
Bit5
Bit5
—
—
R
R/W
Bit4
Bit4
—
—
R
Rev. 1.1
SOF
R/W
Bit3
Bit3
—
R
RSTINT
R/W
Bit2
Bit2
—
R
RSUINT
IN1E
R/W
Bit1
Bit1
R
SUSINT
EP0E
R/W
Bit0
Bit0
R
USB Address:
USB Address:
00000011
00000000
Reset Value
Reset Value
0x07
0x06