C8051F326-TB Silicon Laboratories Inc, C8051F326-TB Datasheet - Page 96

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C8051F326-TB

Manufacturer Part Number
C8051F326-TB
Description
BOARD PROTOTYPING W/C8051F326
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet

Specifications of C8051F326-TB

Contents
Board
Processor To Be Evaluated
C8051F326/F327
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F326
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
C8051F326/7
12.5.1. FIFO Access
Each endpoint FIFO is accessed through a corresponding FIFOn register. A read of an endpoint FIFOn
register unloads one byte from the FIFO; a write of an endpoint FIFOn register loads one byte into the end-
point FIFO. When an endpoint FIFO is configured for Split Mode, a read of the endpoint FIFOn register
unloads one byte from the OUT endpoint FIFO; a write of the endpoint FIFOn register loads one byte into
the IN endpoint FIFO.
96
R/W
Bit7
USB Register Definition 12.6. FIFOn: USB0 Endpoint FIFO Access
USB Addresses 0x20–0x21 provide access to the 2 pairs of endpoint FIFOs:
Writing to the FIFO address loads data into the IN FIFO for the corresponding endpoint.
Reading from the FIFO address unloads data from the OUT FIFO for the corresponding
endpoint.
IN/OUT Endpoint FIFO
R/W
Bit6
0
1
R/W
Bit5
R/W
Bit4
FIFODATA
USB Address
0x20
0x21
Rev. 1.1
R/W
Bit3
R/W
Bit2
R/W
Bit1
R/W
Bit0
USB Address:
0x20–0x23
00000000
Reset Value

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