C8051F326-TB Silicon Laboratories Inc, C8051F326-TB Datasheet - Page 114
C8051F326-TB
Manufacturer Part Number
C8051F326-TB
Description
BOARD PROTOTYPING W/C8051F326
Manufacturer
Silicon Laboratories Inc
Type
MCUr
Datasheet
1.C8051F326-TB.pdf
(140 pages)
Specifications of C8051F326-TB
Contents
Board
Processor To Be Evaluated
C8051F326/F327
Interface Type
USB
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
For Use With/related Products
C8051F326
Lead Free Status / Rohs Status
Lead free / RoHS Compliant
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USB Register Definition 12.22. EOUTCSRH: USB0 OUT Endpoint Control High Byte
Bit7:
Bit6:
Bits5–0: Unused. Read = 000000b. Write = don’t care.
Bits7–0: EOCL: OUT Endpoint Count Low Byte
Bits7–2: Unused. Read = 00000b. Write = don’t care.
Bits1–0: EOCH: OUT Endpoint Count High Byte
DBOEN
USB Register Definition 12.24. EOUTCNTH: USB0 OUT Endpoint Count High
USB Register Definition 12.23. EOUTCNTL: USB0 OUT Endpoint Count Low
R/W
Bit7
Bit7
Bit7
—
R
R
DBOEN: Double-buffer Enable
0: Double-buffering disabled for the selected OUT endpoint.
1: Double-buffering enabled for the selected OUT endpoint.
ISO: Isochronous Transfer Enable
This bit enables/disables isochronous transfers on the current endpoint.
0: Endpoint configured for bulk/interrupt transfers.
1: Endpoint configured for isochronous transfers.
EOCL holds the lower 8-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.
EOCH holds the upper 2-bits of the 10-bit number of data bytes in the last received packet in
the current OUT endpoint FIFO. This number is only valid while OPRDY = ‘1’.
ISO
R/W
Bit6
Bit6
Bit6
—
R
R
R/W
Bit5
Bit5
Bit5
—
—
R
R
R/W
Bit4
Bit4
Bit4
—
—
R
R
EOCL
Rev. 1.1
Bit3
Bit3
Bit3
—
—
R
R
R
Bit2
Bit2
Bit2
—
—
R
R
R
Bit1
Bit1
Bit1
—
R
R
R
E0CH
Bit0
Bit0
Bit0
—
R
R
R
USB Address:
USB Address:
USB Address:
00000000
00000000
00000000
Reset Value
Reset Value
Reset Value
0x15
0x16
0x17
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