STEVAL-ISB005V1 STMicroelectronics, STEVAL-ISB005V1 Datasheet - Page 56

• Manufacturer Part Number: STEVAL-ISB005V1
• Description: BOARD EVAL CHARGER ST7260/L6924D
• Manufacturer: STMicroelectronics
• Type: Battery Managementr

Specifications of STEVAL-ISB005V1

• Main Purpose: Power Management, Battery Charger
• Embedded: Yes, MCU, 8-Bit
• Utilized Ic / Part: L6924, ST72F63BK6M1
• Primary Attributes: 1 Cell- Li-Ion / Li-Pol, 5 V (USB Input)
• Secondary Attributes: Powered by Wall Adaptor Also, LED Status Indicators
• Input Voltage: 5 V
• Product: Power Management Modules
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With/related Products: L6924D, ST7260
• Other names: 497-8428

Watchdog timer (WDG)
Note:
56/139
1
2
3
4
5
If the timer clock is an external clock, the formula is:
Where:
Δt
f
Clearing the output compare interrupt request (that is, clearing the OCFi bit) is done by:
1.
2.
The following procedure is recommended to prevent the OCFi bit from being set between
the time it is read and the write to the OC
●
●
●
After a processor write cycle to the OCiHR register, the output compare function is inhibited
until the OCiLR register is also written.
If the OCiE bit is not set, the OCMPi pin is a general I/O port and the OLVLi bit will not
appear when a match is found but an interrupt could be generated if the OCIE bit is set.
In both internal and external clock modes, OCFi and OCMPi are set while the counter value
equals the OCiR register value (see
Figure 33 on page 57
PWM mode.
The output compare functions can be used both for generating external events on the
OCMPi pins even if the input capture mode is also used.
The value in the 16-bit OC
successful comparison in order to control an output waveform or establish a new elapsed
timeout.
Forced output compare capability
When the FOLVi bit is set by software, the OLVLi bit is copied to the OCMPi pin. The OLVi bit
has to be toggled in order to toggle the OCMPi pin when it is enabled (OCiE bit = 1). The
OCFi bit is then not set by hardware, and thus no interrupt request is generated.
The FOLVLi bits have no effect in both one pulse mode and PWM mode.
EXT
Reading the SR register while the OCFi bit is set.
An access (read or write) to the OCiLR register.
Write to the OCiHR register (further compares are inhibited).
Read the SR register (first step of the clearance of the OCFi bit, which may be already
set).
Write to the OCiLR register (enables the output compare function and clears the OCFi
bit).
= Output compare period (in seconds)
= External timer clock frequency (in hertz)
for an example with f
i
R register and the OLVi bit should be changed after each
Δ OCiR = Δt
Figure 32 on page 57
i
R register:
CPU
/4). This behavior is the same in OPM or
*
f
EXT
for an example with f
CPU
ST7260xx
/2 and